zl50232 Zarlink Semiconductor, zl50232 Datasheet - Page 19

• Manufacturer Part Number: zl50232
• Description: 32 Channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

7.0
Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual
ported memory is mapped into segments on a “per channel” basis to monitor and control each individual echo
canceller and associated PCM channels. For example, in Normal configuration, echo canceller #5 makes use of
Echo Canceller B from group 2. It occupies the internal address space from 0A0
PCM channel #5 on all serial PCM I/O streams.
As illustrated in Table 3, the “per channel” registers provide independent control and status bits for each echo
canceller. Figure 10 shows the memory map of the control/status register blocks for all echo cancellers.
When Extended Delay or Back-to-Back configuration is selected, Control Register 1 of ECA and ECB and Control
Register 2 of the selected group of echo cancellers require special care. Refer to the Register description section.
Table 4 is a list of the channels used for the 16 groups of echo cancellers when they are configured as Extended
Delay or Back-to-Back.
7.1
For a given group (group 0 to 15), 2 PCM I/O channels are used. For example, group 1 Echo Cancellers A and B,
channels 2 and 3 are active.
7.2
For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel
carries quiet code. For example, group 2, Echo Canceller A (Channel 4) will be active and Echo Canceller B
(Channel 5) will carry quiet code.
Normal Configuration
Extended Delay Configuration
Memory Mapped Control and Status Registers
Group
0
1
2
3
4
5
6
7
Table 4 - Group and Channel Allocation
Channels
Zarlink Semiconductor Inc.
12, 13
14, 15
10, 11
0, 1
2, 3
4, 5
6, 7
8, 9
ZL50232
19
Group
10
12
13
14
15
11
8
9
Channels
16, 17
18, 19
20, 21
22, 23
24, 25
26, 27
28, 29
30, 31
hex
to 0BF
hex
and interfaces to
Data Sheet