zl50232 Zarlink Semiconductor, zl50232 Datasheet
zl50232
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zl50232 Summary of contents
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... Group 15 ECA/ECB ECA/ECB ECA/ECB ECA/ECB Microprocessor Interface D7-D0 IRQ TMS TDI TDO TCK TRST Figure 1 - ZL50232 Device Overview 1 Zarlink Semiconductor Inc. ZL50232 Data Sheet March 2006 Ordering Information 100 Pin LQFP Trays 208 Ball PBGA Trays 100 Pin LQFP* Trays, Bake & Drypack ...
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... ECB) which can be configured to provide two channels of 64 milliseconds or one channel of 128 milliseconds echo cancellation. This provides 32 channels of 64 milliseconds to 16 channels of 128 milliseconds echo cancellation or any combination of the two configurations. The ZL50232 supports ITU-T G.165 and G.164 tone disable requirements ...
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... Sout V IC0 V SS DD1 SS V Rin V Rout V Sin SS SS DD1 DD2 SS DD1 SS DD1 DD2 DD1 SS DD1 SS DD1 ZL50232GD ...
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... Back-to-Back Configuration 3.3 Extended Delay Configuration 4.0 Echo Canceller Functional States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 Mute 4.2 Bypass 4.3 Disable Adaptation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 Enable Adaptation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.0 ZL50232 Throughput Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.0 Serial PCM I/O channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 Serial Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.0 Memory Mapped Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1 Normal Configuration 7.2 Extended Delay Configuration 7.3 Back-to-Back Configuration 7.4 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 ...
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... Figure 1 - ZL50232 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - 100 Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 3 - 208 Ball LBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 4 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5 - Disable Tone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6 - Normal Device Configuration (64 ms Figure 7 - Back-to-Back Device Configuration (64 ms Figure 8 - Extended Delay Configuration (128 ms Figure 9 - ST-BUS and GCI Interface Channel Assignment for 2 Mbps Data Streams . . . . . . . . . . . . . . . . . . . . . 18 Figure 10 - Memory Mapping ...
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... Table 1 - Comparison of NLP Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 2 - Quiet PCM Code Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3 - Memory Mapping of Per Channel Control and Status Registers Table 4 - Group and Channel Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5 - Comparison of the NLP Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 ZL50232 List of Tables 6 Zarlink Semiconductor Inc. Data Sheet ...
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... P4, P6, P8, P10, P15, R4, R6, R8, R10, R12, T5, T12 V C6, D6, J3, J4, N12, DD2 P12, G13, G14 IC0 E15, F15, A12, A10, A6, A2, B1, B3, C1, C2, D2, E2, J2, K2, R1 ZL50232 Change Updated Ordering Information 100 Pin LQFP 5, 18, 32, Ground. 42, 56, 69, 81, 98 27, 48, 77, Positive Power Supply. Nominally 3.3 V (I/O Voltage). ...
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... DTA D0..D7 T2,T4,T6,T8,T9,T11, T13,T15 A0..A10 P16,N16,M16,L16,K16, J16,H16,G16,F16,E16, D16 ODE B13 Sout A8 Rout B9 Sin B11 ZL50232 100 Pin LQFP 24, 25, 26, No connection. These pins must be left open for normal 44, 45, 46, operation. 47, 49, 51, 52, 53, 54, 55, 73, 74, 75, 76, 78, 79, 80, 82, 83, 84, 85, 89, 99, 50 Interrupt Request (Open Drain Output). This output goes low 9 when an interrupt occurs in any channel ...
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... Test Reset (3.3 V Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up or held low, to ensure that the ZL50232 is in the normal functional mode. This pin is pulled by an internal pull-down when not driven. 8 Device Reset (Schmitt Trigger Input). An active low resets the device and puts the ZL50232 into a low-power stand-by mode ...
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... Device Overview The ZL50232 architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers, Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, Extended Delay or Back-to-Back configurations. In Normal configuration, a group of echo cancellers provides two channels echo cancellation, which run independently on different channels. In Extended Delay configuration, a group of echo cancellers achieves 128 ms of echo cancellation by cascading the two echo cancellers (A & ...
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... Detector Threshold (DTDT) should be set to 0.5 (-6 dB). However, in order to achieve additional guardband, the DTDT is set internally to 0.5625 (-5 dB). In some applications the return loss can be higher or lower than 6 dB. The ZL50232 allows the user to change the detection threshold to suit each application’s need. This threshold can be set by writing the desired threshold value into the DTDT register ...
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... Non-Linear Processor (NLP) After echo cancellation, there is always a small amount of residual echo which may still be audible. The ZL50232 uses Zarlink’s patented Advanced NLP to remove residual echo signals which have a level lower than the Adaptive Suppression Threshold (TSUP in G.168). This threshold depends upon the level of the Rin (Lrin) reference signal as well as the programmed value of the Non-Linear Processor Threshold register (NLPTHR) ...
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... If the disable tone is present for a minimum of 400 ms, with or without phase reversal, the Tone Detector will trigger. The ZL50232 has two Tone Detectors per channels (for a total of 64) in order to monitor the occurrence of a valid disable tone on both Rin and Sin. Upon detection of a disable tone, TD bit of the Status Register will indicate logic high and an interrupt is generated (i ...
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... Adjustable Level Pads The ZL50232 provides adjustable level pads at Rin, Rout, Sin and Sout. This setup allows signal strength to be adjusted both inside and outside the echo path. Each signal level may be independently scaled with anywhere from + -12 dB level steps. Level values are set using the Gains register. ...
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... Device Configuration The ZL50232 architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers which can be individually controlled (Echo Canceller A (ECA) and Echo Canceller B (ECB)). They can be set in three distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figures 6, 7, and 8. ...
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... In Normal and in Extended Delay configurations, writing a “1” into the MuteR bit replaces Rin with quiet code which is applied to both the Adaptive Filter and Rout. Writing a “1” into the MuteS bit replaces the Sout PCM data with quiet code. +Zero (quiet code) ZL50232 channel A Sin + - ...
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... The input and output data rate of the ST-BUS and GCI bus is 2.048 Mbps. The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The ZL50232 automatically detects the presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling edge of the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three quarters of the way into the bit cell (See Figure 12) ...
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... Reserved 19h 18h NLPTHR 1Bh 1Ah Step Size, MU 1Dh 1Ch Gains 1Fh 1Eh Reserved Table 3 - Memory Mapping of Per Channel Control and Status Registers ZL50232 125 µsec Channel 1 Channel 30 Base Echo Canceller B Address + MS LS Byte Byte - 20h Control Reg 1 - 21h ...
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... Extended Delay Configuration For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel carries quiet code. For example, group 2, Echo Canceller A (Channel 4) will be active and Echo Canceller B (Channel 5) will carry quiet code. ZL50232 Channels Group 0, 1 ...
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... Power Up Sequence On power up, the RESET pin must be held low for 100 µs. Forcing the RESET pin low will put the ZL50232 in power down state. In this state, all internal clocks are halted, D<7:0>, Sout, Rout, DTA and IRQ pins are tristated. The 16 Main Control Registers, the Interrupt FIFO Register and the Test Register are reset to zero. ...
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... Since the Narrow Band Detector is “ON” regardless of the functional state of Echo Canceller it is recommended that the Echo cancellers are reset before any call progress tones are applied. ZL50232 System Powerup Reset Held Low µ ...
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... Test Access Port (TAP) controller. JTAG inputs are 3.3 V compliant only. 8.1 Test Access Port (TAP) The TAP provides access to many test functions of the ZL50232. It consists of four input pins and one output pin. The following pins are found on the TAP. • ...
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... Instruction Register In accordance with the IEEE 1149.1 standard, the ZL50232 uses public instructions. The JTAG Interface contains a 3-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that will operate while the instruction is current, and to define the serial test data register path, which is used to shift data between TDI and TDO during data register scanning ...
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... Characteristics are over recommended operating conditions unless otherwise stated. ° ‡ Typical figures are =3.3 V and are for design aid only: not guaranteed and not subject to production testing. DD1 * Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage ( ZL50232 Symbol V DD_IO ) V DD_CORE ...
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... Characteristics are over recommended operating conditions unless otherwise stated. ° ‡ Typical figures are 3.3 V and for design aid only: not guaranteed and not subject to production testing. DD1 * Note1: High Impedance is measured by pulling to the appropriate rail with R ZL50232 Sym. Level V 0.5V TT DD1 V 0 ...
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... Characteristics are over recommended operating conditions unless otherwise stated. ° ‡ Typical figures are 3.3 V and for design aid only: not guaranteed and not subject to production testing. DD1 ZL50232 - Voltages are with respect to ground (V ‡ Sym. Min. Typ. Max. ...
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... SOD Sout/Rout Bit 7, Channel 31 Bit 0, Channel 0 t SIS Sin/Rin Bit 7, Channel 31 Bit 0, Channel 0 Figure 13 - GCI Interface Timing at 2.048 Mbps ODE Sout/Rout Figure 14 - Output Driver Enable (ODE) ZL50232 Bit 6, Channel 0 Bit 5, Channel SIS SIH Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 ...
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... MCLK DS CS R/W A0-A10 D0-D7 READ D0-D7 WRITE DTA IRQ Figure 16 - Motorola Non-Multiplexed Bus Timing ZL50232 t MCH t MCL Figure 15 - Master Clock t CSS t RWS t ADS VALID ADDRESS t DDR VALID READ DATA t DSW VALID WRITE DATA t AKD t IRD 28 Zarlink Semiconductor Inc. Data Sheet CSH ...
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... When low, the echo canceller dynamically adapts to the echo path characteristics. 1 Bits marked as “1” or “0” are reserved bits and should be written as indicated. 0 Control Register 1 (Echo Canceller B) Bit reserved bit and should be written “0”. ZL50232 R/W Address: 00 hex Bit 5 Bit 4 ...
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... When high, data on Rout is muted to quiet code. When low, Rout carries active code. Note: In order to correctly write to Control Register 1 and 2 of ECB necessary to write the data twice to the register, one immediately after another. The two writes must be separated by at least 350ns and no more than 20 us. ZL50232 ECA: Control Register 2 ECB: Control Register 2 ...
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... ECB: Decay Step Size Control Register (SSC) Bit 7 Bit 6 Bit Note: Bits marked with “0” are reserved bits and should be written “0” ZL50232 ECA: Status Register ECB: Status Register Bit 4 Bit 3 Bit 2 Reserve Reserve Reserve ECA: Flat Delay Register (FD) ...
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... SS taps (see SSC Length (512 or 1024) - [Decay Step Number (NS For example and SSC 7-0 4 512 - [4 x (4x2 )] = 256 taps for a filter length of 512 taps. ZL50232 FIR Filter Length (512 or 1024 taps) Figure 17 - The MU Profile x 8 taps. For example then MU=2 7-0 7-0 is: 0 ≤ FD 7-0 is zero ...
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... The Table 5 below is the same as Table 1 shown on page 12) Feature NLP Selection Reject uncancelled echo as noise Reject double-talk as noise Noise level estimator ramping scheme Noise level ramping rate Noise level scaling ZL50232 ECA: Control Register 3 ECB: Control Register 3 Bit 4 Bit 3 RingClr Reserve Functional Description of Register Bits Register or Bit(s) ...
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... Noise level estimator ramping rate. When InjCtrl = 1, a lower value will give faster ramping. When InjCtrl = 0, a higher value will give faster ramping. The default value of 5 G.168 compliance with InjCtrl = 1. A value of C ZL50232 ECA: Control Register 4 ECB: Control Register 4 ...
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... These peak detector registers allow the user to monitor the send in (Sin) peak signal level. The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1. ZL50232 Bit 4 Bit 3 ...
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... DTDT7 DTDT6 DTDT5 This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2’s complement linear value defaults to 4800 0 dB. The high byte is in Register 2 and the low byte is in Register 1. ZL50232 Bit 4 Bit 3 EP12 EP11 Bit 4 ...
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... MU7 MU6 MU5 Functional Description of Register Bits This register allows the user to program the level of MU bit 2’s complement value which defaults to 4000 = 1.0 The maximum value is 7FFF hex is in Register 1. ZL50232 (NLPTHR) (NLPTHR) Bit 4 Bit 3 Bit 2 NLP12 NLP11 NLP10 ...
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... Note that the -12 dB PAD bit in Control Register 1 provides attenuation in the Rin to Rout path, and will override the settings in Gains. ZL50232 ECA: Gains Register 2 ECB: Gains Register 2 Bit 4 Bit 3 Bit 2 Rin0 0 Rout2 ECA: Gains Register 1 ...
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... Address+00 to Base Address+3F hex coefficients. Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers for their specific application. ZL50232 R/W Address: 400 Bit 4 Bit 3 Bit 2 MTDBI MTDAI ...
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... A and B execute their initialization routine which presets their registers, Base Address+00 to Base Address+3F hex coefficients. Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers for their specific application. ZL50232 hex Bit 4 Bit 3 Bit 2 MTDBI MTDAI ...
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... Test IRQ: Useful for the application engineer to verify the interrupt service routine. When high, any change to MTDBI and MTDAI bits of the Main Control Register will cause an interrupt and its corresponding channel number will be available from the Interrupt FIFO Register. When low, normal operation is selected. ZL50232 Interrupt FIFO Register R/W Address: 410 Bit 4 ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...