mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 60

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

7.2.1
The pin (TxDL, TxDLC, RxDL and RxDLC) enable bits Sa4SS to Sa8SS of control register address Y08 determine
the type of data link access enabled. A ’01’ code enables the corresponding data link (DL) bits to be sourced to and
from the RxDL and TxDL pins, by enabling the corresponding pulses in either gapped clocks or enable low signals
provided at the RxDLC and TxDLC pins. The option of either gapped clock or enable signal is selected by control bit
DLCK (register address Y08). The data link bits are transmitted on and received from the PCM30 link, in the
national bit (Sa4 to Sa8) positions (four to eight of timeslot zero) of the Non-Frame Alignment Signal (NFAS)
frames. The gapped clock rate will be either 4, 8, 12, 16 or 20 kb/s, and will depend on the number of Sa bits
enabled by SA#SS bits (register Y08). Similarly the enable pulse width(s) will also depend on the number of Sa bits
enabled.
7.2.1.1
Data to be transmitted onto the line in the S
Although the aggregate clock rate equals the bit rate, it has a nominal pulse width of 244 ns, and it clocks in the
TxDL as if it were a 2.048 Mbit/s data stream. The clock can only be active during bit times 4 to 0 of the ST-BUS
frame. The TxDL input signal is clocked into the MT9072 by the falling edge of TxDLC which occurs about 3/4 into
the ST-BUS bit cell. If DL bits are selected to be accessed through the DL pins, then all other programmed functions
for those S
7.2.1.2
The RxDLC clock and enable signal is derived from the receive extracted clock (EXCLi) and is aligned with the
receive data link output RxDL. The HDB3 decoded receive data, at 2.048 Mbit/s, is clocked out of the device on the
RxDL pin with the falling edge of EXCLi. In order to facilitate the attachment of this data stream to a Data Link
controller, the clock signal RxDLC consists of positive pulses, of nominal width of 244 ns, during the S
that are selected for the data link, with the rising edge aligned with the middle of the bit cell. No DL data will be lost
or repeated when a receive frame slip occurs as the DL data does not pass through the elastic buffer. The output
signal at the RxDLC pin may be either a clock or an enable signal as programmed by the DLCK control bit (register
address Y08). See Figures 62 & 63 for timing requirements.
7.2.1.3
In this case, the TxDLC pin is used for both DL data transmitted on the PCM30 link and DL data received on the
PCM30 link. However, instead of using the non-buffered data output at the RxDL pin, the buffered DSTo output data
is used. The clock at the TxDLC pin clocks data from the DSTo ST-BUS stream into an external controller, or the
enable signal at the TxDLC pin enables a 2.048 Mbit/s clock which clocks data from the DSTo ST-BUS stream into
an external controller. Since a common clock is used for both transmit and receive, a simpler data controller may be
used such as the MT8952B. However, DL data will be lost or repeated when a receive frame slip occurs, as the DL
data does pass through the elastic buffer. See Figures 59 - 60 for timing requirements.
7.2.2
When the National Bit Buffer transmit data registers access is enabled, the settings of 40 data bits in 5 registers
(address YB0-YB4) determine the Data Link (DL) output on the PCM30 link corresponding to bit positions Sa4-8
over one complete CRC-4 Multiframe. The CRC-4 alignment status bit CALN (register address Y11) and
corresponding maskable interrupt status bit CALNI (register address Y36) indicate the beginning of every received
CRC-4 multiframe. Data for DL transmission should be written to the National Bit Buffer transmit data registers
immediately following the CALN status indication (during basic frame 0) and before the start of basic frame 1.
Table 18 illustrates the organization of the MT9072 transmit and receive national bit buffers. Each row is an
addressable byte of the MT9072 national bit buffer, and each column contains the national bits of an odd numbered
frame of each CRC-4 Multiframe. The transmit and receive national bit buffers are located at addresses YB0 to YB4
and YC0 to YC4 respectively.
E1 Data Link (DL) Pin Access
E1 Data Link (DL) National Bit Buffer Access
E1 Data Link (DL) Pin Data Transmitted on PCM30
E1 Data Link (DL) Pin Data Received on PCM30 - With No Elastic Buffer
E1 Data Link (DL) Pin Data Received on PCM30 - With Elastic Buffer
a
bit positions are overridden. See Figures 59 & 60 for timing requirements.
a
Zarlink Semiconductor Inc.
bit position is clocked in from the TxDL pin with the TxDLC clock.
MT9072
60
Data Sheet
a
bit cell times