mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 45

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

5.0
5.1
DS1 trunks contain 24 bytes of serial voice/data channels bundled with an overhead bit - the S-bit. The S-bit
contains a fixed repeating pattern used to enable DS1 receivers to delineate frame boundaries. S-bits are inserted
once per frame at the beginning of the transmit frame boundary. The DS1 frames are further grouped in bundles of
frames, generally 12 (for D4 applications) or 24 frames deep (for ESF - extended superframe applications). The
registers for controlling and observing the framing algorithms are presented in the Table 7.
Register
Address
Y2C
Y1A
Y2A
Y2B
Y00
Y10
Y16
Y17
Y19
Y24
Y28
Y34
Y44
T1 Framing
Framing
Framing Mode Select
Synchronization and Alarm
Status Word.
MFOOF Counter
Framing Bit Error Counter
CRC-6 Error Counter
Out of Frame Counter and
Change of Frame Counter
Receive Sync and Alarm Latch
Framing Bit Error Count Latch
CRC-6 Error Counter Latch
Out of Frame Counter Latch and
Change of Frame Counter Latch
MFOOF Counter Latch
Receive Sync Interrupt Status
Register
Receive Sync Interrupt Status
Register Mask
Table 7 - Registers Related to Framing Mode for the MT9072 (T1)
Register
Zarlink Semiconductor Inc.
This register is used for selecting the different framing modes
from ESF to D4 or T1DM. The register is also used for selecting
reframe criteria.
This register provides the real time status of the receive framing
algorithm as to basic frame synchronization and multiframe
synchronization.
This status register increments every 1.5 msec for D4 mode or
every 3 msec for ESF mode when the basic frame
synchronization is lost.
This counter counts the Ft errors in ESF mode and Ft+Fs error in
D4 and T1DM.
This counter counts the CRC-6 errors by comparing the
calculated CRC-6 with the CRC-6 bits in the ESF frame.
The out of frame counter is incremeted with every loss of receive
frame synchronization. The change of frame counter is
incremented with every shift in the frame alignment position.
This register contains latched bits for events related to framing
such as framing bit errors.
This counter is a latched version of Y17, the value of this counter
is updated every 1 sec.
This counter is a latched version of Y19, the value of this counter
is updated ever 1 sec.
This counter is a latched version of Y19, the value of this counter
is updated ever 1 sec.
This counter is a latched version of Y16, the value of this counter
is updated ever 1 sec.
This register captures interrupt events related to the receiver
framer such as Framing Bit error. Interrupts can be generated by
setting appropriate masks.
This mask corresponds to the Y34 status register. Writing a “0”
unmasks an interrupt.
MT9072
45
Description
Data Sheet