zl30116 Zarlink Semiconductor, zl30116 Datasheet - Page 27

• Manufacturer Part Number: zl30116
• Description: Sonet/sdh Low Jitter System Synchronizer
• Manufacturer: Zarlink Semiconductor

(Hex)
Addr
5C
5D
5A
5B
5E
5F
56
57
58
59
60
61
62
63
64
65
66
67
sdh_fp0_freq
sdh_fp0_type
sdh_fp0_offset_0
sdh_fp0_offset_1
sdh_fp0_offset_2
sdh_fp1_freq
sdh_fp1_type
sdh_fp1_fine_offset_0
sdh_fp1_fine_offset_1
sdh_fp1_coarse_offset
diff_ctrl
diff_sel
fb_control
fb_offset_fine
reserved
ref_freq_mode_0
ref_freq_mode_1
custA_mult_0
Register
Name
Table 5 - Register Map (continued)
N * 8 kHz Reference Control
Reset
Value
(Hex)
External Feedback Configuration
Differential Output Configuration
A3
05
23
00
00
00
03
03
00
00
00
53
80
F5
00
00
00
Zarlink Semiconductor Inc.
ZL30116
Bits [7:0] of the programmable frame pulse
Bits [21:16] of the programmable frame pulse
Control register to set whether to use auto
Control register to set whether to use auto
Control register for the [7:0] bits of the custom
Control register to select the sdh_fp0 frame
pulse frequency
Control register to select fp0 type
phase offset in multiples of 1/311.04 MHz
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
phase offset in multiples of 8 kHz cycles
Control register to select sdh_fp1 frame pulse
frequency
Control register to select fp1 type
Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
Programmable frame pulse phase offset in
multiples of 8 kHz cycles
Control register to enable diff0, diff1
Control register to select the diff0 and diff1
frequencies
Control register to enable fb_clk and the FB
PLL, int/ext feedback select
Control register for the output/output phase
alignment fine tuning
detect, CustomA or CustomB for ref0 to ref3
detect, CustomA or CustomB for ref4 to ref7
configuration A. This is the N integer for the
N*8kHz reference monitoring.
27
Description
Data Sheet
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W