zl30109 Zarlink Semiconductor, zl30109 Datasheet - Page 20

• Manufacturer Part Number: zl30109
• Description: Ds1/e1 System Synchronizer With 19.44 Mhz Output
• Manufacturer: Zarlink Semiconductor

4.5
The active reference input (REF0, REF1) is selected by the REF_SEL pin as shown in Table 5. If the logic value of
the REF_SEL pin is changed when the DPLL is in Normal mode, the ZL30109 will perform a hitless reference
switch.
When the REF_SEL inputs are used to force a change from the currently selected reference to another reference,
the action of the LOCK output will depend on the relative frequency and phase offset of the old and new references.
Where the new reference has enough frequency offset and/or TIE-corrected phase offset to force the output
outside the phase-lock-window, the LOCK output will de-assert, the lock-qualify timer is reset, and LOCK will stay
de-asserted for the full lock-time duration. Where the new reference is close enough in frequency and
TIE-corrected phase for the output to stay within the phase-lock-window, the LOCK output will remain asserted
through the reference-switch process.
REF_DIS=1: Current selected reference disrupted (see Figure 3). This is an internal signal.
REF_CH= 1: Reference change, a change in the REF_SEL pin. This is an internal signal.
Reference Selection
RST
(HOLDOVER=1)
REF_CH=0 and
HMS=0
REF_DIS=0 and
REF_SEL
Figure 10 - Mode Switching in Normal Mode
(input pin)
Holdover
0
1
Table 5 - Reference Selection
Zarlink Semiconductor Inc.
(REF_DIS=0 and HMS=1) or
ZL30109
REF_DIS=1
Input Reference Selected
(HOLDOVER=0)
20
REF_DIS=1
REF_DIS=0
REF_CH=1
Normal
REF0
REF1
REF_CH=1
(HOLDOVER=1)
TIE Correction
Data Sheet