zl30109 Zarlink Semiconductor, zl30109 Datasheet - Page 11

• Manufacturer Part Number: zl30109
• Description: Ds1/e1 System Synchronizer With 19.44 Mhz Output
• Manufacturer: Zarlink Semiconductor

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Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single
cycle and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the
reference input signal when the failures are present for more than 2.5 s. The single cycle and coarse frequency
failures must be absent for 10 s to let the timer re-qualify the input reference signal as valid. Multiple failures of less
than 2.5 s each have an accumulative effect and will disqualify the reference eventually. This is illustrated in Figure
4.
REF0 /
REF1
Reference Frequency Detector: This detector determines whether the frequency of the reference clock is
2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz and provides this information
to the various monitor circuits and the phase detector circuit of the DPLL.
Precise Frequency Monitor: This circuit determines whether the frequency of the reference clock is within
the applicable out-of-range limits selected by the OOR_SEL pin, see Figure 5, Figure 6 and Table 1. It will
take the precise frequency monitor up to 10 s to qualify or disqualify the input reference.
Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals of
approximately 30 µs to quickly detect large frequency changes.
Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large phase
hits or the complete loss of the clock.
Reference Frequency
Precise Frequency
Coarse Frequency
Single Cycle
Detector
Monitor
Monitor
Monitor
Figure 3 - Reference Monitor Circuit
OR
Zarlink Semiconductor Inc.
ZL30109
dis/requalify
11
timer
OR
REF_DIS= reference disrupted.
This is an internal signal.
REF_DIS
Mode select
state machine
Data Sheet
HOLDOVER
REF_FAIL0 /
REF_FAIL1