zl30109 Zarlink Semiconductor, zl30109 Datasheet - Page 12

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zl30109

Manufacturer Part Number
zl30109
Description
Ds1/e1 System Synchronizer With 19.44 Mhz Output
Manufacturer
Zarlink Semiconductor
Datasheet

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When the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output
signal locked to the input signal. Each of the monitors has a built-in hysteresis to prevent flickering of the REF_FAIL
status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the mode
(Holdover/Normal) of the DPLL.
C20: 20 MHz master clock on OSCi
current REF
HOLDOVER
REF_FAIL
timer
C20 Clock Accuracy
+32 ppm
-32 ppm
2.5 s
0 ppm
Figure 5 - DS1 Mode Out-of-Range Limits (OOR_SEL=0)
-200
Figure 4 - Behaviour of the Dis/Re-qualify Timer
-150
-115
-100
-96
-83
10 s
Zarlink Semiconductor Inc.
SCM or CFM failure
-64
-51
-50
C20
-32
ZL30109
-32
C20
0
0
0
0
12
C20
32
32
50
64
51
83
96
100
115
150
200
Out of Range
In Range
Out of Range
In Range
Out of Range
In Range
Frequency offset [ppm]
Data Sheet

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