ml70q5110la Oki Semiconductor, ml70q5110la Datasheet
ml70q5110la
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ml70q5110la Summary of contents
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... Bluetooth Baseband Controller IC GENERAL DESCRIPTION The ML70Q5110LA is a CMOS digital IC for use in 2.4 GHz band Bluetooth™ systems. This IC incorporates the ARM7TDMI as the CPU core, features a highly expandable architecture, and supports the interfaces for a variety of applications. Used in conjunction with the ML7050LA (Bluetooth RF Transceiver IC) and the OKI Bluetooth Protocol Stack Software, data/voice communications are possible while maintaining interconnectivity with other Bluetooth systems ...
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... DI V Includes VDI 0 — 0 GND 2 1 3.6 V — < V < V – 2/26 FEDL70Q5110LA-01 ML70Q5110LA Rating Unit –0.3 to +4.5 V –0.3 to +4.5 V 1.35 W –55 to 150 °C Typ. Max. Unit 3.3 3.6 V — 3.6 V — 0.8 V — 85 °C Typ. Max. Unit 3 ...
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... VDD MA6 MA3 MA17 GND MA9 MA7 MA0 MA14 MA12 MA10 GND MA5 GND MA13 MA8 MA4 MA1 TOP VIEW 3/26 FEDL70Q5110LA-01 ML70Q5110LA SCLK GND TMS TCK SEL TEST_L AVDD1 TRST GND VDD SCLK REG GND REMAP1REGOUT GND MBS0 MOE1 ...
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... When the transmit clock is used by a clock — F2 (RXC) that is generated from the receive data, set TXCSEL(Pin# A10 and connect to RXC(Pin# B2). Bluetooth transmit clock setting pin — A10 L: Select 1 MHz divided by internal PLL. H: Select TXC_IN input signal. 4/26 FEDL70Q5110LA-01 ML70Q5110LA Description ...
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... MA16: M4; MA15: K5; MA14: M5 MA4: N8; MA3: K9; MA2: M10; MA1: N9; MD5: K13; MD4: J11; MD0: H12 5/26 FEDL70Q5110LA-01 ML70Q5110LA Description “01” MHz “10” MHz “11” : Forbidden “01” Stacked Flash ROM “10” External MCS1 device “11” External MCS0 device Description MA8: N7 ...
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... GPIO7) Serial data input — L1 (Pin shared with GPIO6) Clock for serial data output (Pin shared — M2 with GPIO5) During initialization: input Clock for serial data input (Pin shared with — M1 GPIO4) During initialization: input 6/26 FEDL70Q5110LA-01 ML70Q5110LA Description Description Description ...
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... Placement L G2 PCM data output — G4 PCM data input PCM sync signal (8 kHz) — H3 During initialization: input (can be switched by an internal register) PCM clock (64 kHz/128 kHz) — G3 During initialization: input (can be switched by an internal register) 7/26 FEDL70Q5110LA-01 ML70Q5110LA Description Description Description Description ...
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... REGOUT pin: F12) — C11 — E11 Analog block ground pin (Connect to REGGND pin: F13) — A11 — E12 Regulator power pin (3.0 to 3.6 V) — F13 Regulator ground pin — F12 Regulator output — E10 Regulator reference voltage tuning 8/26 FEDL70Q5110LA-01 ML70Q5110LA Description Description ...
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... The circuit is subject to change according to the specific LSI board design. Please contact Oki Electric Industry Co., Ltd. for detailed information. 10 0.018 1 0.1 0 0.1 0.1 GND Capacitors shold locate close to LSI pins. Unit: F Example for ML70Q5110LA voltage supply circuit 9/26 FEDL70Q5110LA-01 ML70Q5110LA V DD GND Feed lines should be separated from LSI pins. ...
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CLK GEN 32 kB RAM Timer Default Slave I/F I/F IRC 3ch APB Ctl TIMER I/F I/F I/F I/F I/F PCM/ BT-BB RFLSI USB Core CVSD PCM Codec AMBA APB System XMC- SIO APB Ctl Control (BIU) AMBA AHB 2 ...
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... Control of reset of each peripheral STOP/HALT control External clock selection control CIO switching function Watchdog timer function (interrupt/reset) 3 types of count stop functions Timer Block 3 channels 18 bit timer counter for each channel Iterrupt at counter overflow Independent mode for each channel (one shot/interval/free run) 11/26 FEDL70Q5110LA-01 ML70Q5110LA ...
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... Payload processing (FEC decoding, descrambling, encryption decoding, CRC judgement, payload separation) Security - Various key generation functions (initialization, link key, encryption key) - Certification function - Encryption function Tx SCO Buffer Packet Composer Tx ACL Buffer FHCNT Security Timing Rx SCO Buffer Packet Decomposer Rx ACL Buffer 12/26 FEDL70Q5110LA-01 ML70Q5110LA RF LSI TXD RF CNT CNT RXD ...
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... Modem control based on CTS, DCD, and DSR Programmable serial interface 5-, 6-, 7-, 8-bit characters Generation and verification of odd parity, even parity parity 1, 1. stop bits Programmable Baud Rate Generator (1200 bps to 921.6 kbps) Error servicing for parity, overrun, and framing errors 13/26 FEDL70Q5110LA-01 ML70Q5110LA ...
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... PCMSYMC/PCMCLK I/O can be switched (in the input state after initialization) GPIO Block All 16 bits Input/Output selection possible for each bit Interrupts can be used for all bits Interrupt masks and interrupt modes can be set for all bits In the input state immediately after a reset 14/26 FEDL70Q5110LA-01 ML70Q5110LA ...
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... MHz “11” : Forbidden HCI Transport Selection HCI is selected (USB/UART) according to the logical value of GPIO0 at initial powerup of ML70Q5110LA. GPIO0 = L : UART is used as HCI. GPIO0 = H : USB is used as HCI. : Forbidden : Stack Flash ROM Devices connected to external MCS1 : Devices connected to external MCS0 : 15/26 FEDL70Q5110LA-01 ML70Q5110LA ...
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... CVSD (initial setting)/ -law/A-law - Interface coding Linear (initial setting)/ -law/A-law - PCM format (data width of one PCM Linear sample) 8-bit (initial setting)/14-bit/16-bit - Serial interface format Short frame (initial setting)/long frame - Application interface mode PCM Codec I/F (initial setting)/APB I/F 16/26 FEDL70Q5110LA-01 ML70Q5110LA ...
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... OKI Semiconductor External Memory ML70Q5110LA specifications for the devices that are connected to MCS0 and MCS1 are explained below. When the device is connected to MCS0 memory bank - Bus width bits - Byte access control: MBS*/MWE - Supported devices: Normal SRAM, Flash Memory, Page mode Flash memory ...
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... Data OFF time clock cycles [*3] Address set-up time clock cycles [*4] Write data set-up time: 0 clock cycles (IOWRTYPE = clock cycles (IOWRTYPE = 1) [*3] [*1] [*2] [*3] [*4] [*1] [*2] 1 clock fixed 18/26 FEDL70Q5110LA-01 ML70Q5110LA [*1] 1 clock fixed [*1] 1 clock fixed ...
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... Connect MA0 to device A0 for devices that have an 8-bit data bus. - MOE0 is the AND signal for MCS0 and MRE. Perform an open process when this is not in use. - MOE1 is the AND signal for MCS1 and MRE. Perform an open process when this is not in use. 19/26 FEDL70Q5110LA-01 ML70Q5110LA ...
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... Open Open Open Open Open Open Open Open Open Open Pull Pull Pull Pull Pull Pull Pull Pull Pull 20/26 FEDL70Q5110LA-01 ML70Q5110LA Comments Comments ...
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... Open Open Open Open Open Open Open Open Only use when connecting to a device that has only one, but not both of MCS* or MRE. Open Open Open Open Open Open Open Open Open Open Open Open 21/26 FEDL70Q5110LA-01 ML70Q5110LA Comments Comments Comments Comments ...
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... Pull down or GND TEST_H TEST_PU VTM RESET RESET_OUT NC The unused pin configurations are subject to change according to the specific application. Please contact Oki Electric Industry Co., Ltd. for detailed board layout information. Pull Open Open Pull Open Open 22/26 FEDL70Q5110LA-01 ML70Q5110LA Comments ...
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... Master clock setting for ML7050LA Sets the link control information. Comments 0: -law, 1: A-law, 2: Linear 0: 9600 bps 1: 19.2 kbps 2: 38.4 kbps 3: 56 kbps 4: 115.2 kbps 5: 230.4 kbps 6: 345.6 kbps 7: 57.6 kbps 8: 460.8 kbps 9: 921.6 kbps Unit: 625 sec 12: 12 MHz 13: 13 MHz 16: 16 MHz 23/26 FEDL70Q5110LA-01 ML70Q5110LA ...
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... Package material Ball material Package weight (g) Rev. No./Last Revised 24/26 FEDL70Q5110LA-01 ML70Q5110LA (Unit: mm) Epoxy resin Sn/Pb 0.3 TYP. 1/Aug.25,1999 ...
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... OKI Semiconductor REVISION HISTORY Document Date No. FEDL70Q5110LA-01 Sep.2, 2002 Page Previous Current Edition Edition – – Final edition 1 25/26 FEDL70Q5110LA-01 ML70Q5110LA Description ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd. 26/26 FEDL70Q5110LA-01 ML70Q5110LA ...