ia186eb Innovasic Semiconductor Inc., ia186eb Datasheet - Page 25

• Manufacturer Part Number: ia186eb
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186EB/IA188EB
8-Bit/16-Bit Microcontrollers
Table 7. IA186EB Pin/Signal Descriptions (Continued)
refresh_n
bhe_n is
plexed
Signal
bhe_n
multi-
bclk0
bclk1
busy
with
ale
test_n/busy
plexed with
p2.5/bclk0
p2.2/bclk1
refresh_n
bhe_n is
bhe_n
Name
multi-
ale
®
PLCC
54
59
14
6
7
Pin
PQFP
75
41
46
76
3
UNCONTROLLED WHEN PRINTED OR COPIED
LQFP
38
39
46
Page 25 of 82
IA211080314-02
4
9
address latch enable. Output. Active High.
This signal is used to latch the address
information during the address portion of a bus
cycle.
baud clock, Serial Port 0. Input. The bclk0 pin
can be used to provide an alternate clock
source for Serial Port 0. The input clock rate
cannot be greater than one-half the operating
frequency of the IA186EB.
baud clock, Serial Port 1. Input. The bclk1 pin
can be used to provide an alternate clock
source for Serial Port 1. The input clock rate
cannot be greater than one-half the operating
frequency of the IA186EB.
byte high enable. Output. Active Low. When
bhe_n is asserted (low), it indicates that the
bus cycle in progress is transferring data over
the upper half of the data bus.
Additionally, bhe_n and ad0 encode the
following bus information:
ad0
Note: bhe_n is multiplexed with refresh_n.
busy. Input. Active High. When the busy
input is asserted, it causes the IA186EB to
suspend operation during the execution of the
Intel 80C187 Numerics Coprocessor
instructions. Operation resumes when the pin
is sampled low.
0
0
1
1
bhe_n
0
1
0
1
Description
Bus Status
Word Transfer
Even Byte Transfer
Odd Byte Transfer
Refresh Operation
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January 14, 2009
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