bs62lv2005si Brillance Semiconductor, bs62lv2005si Datasheet

bs62lv2005si

Manufacturer Part Number

bs62lv2005si

Description

Very Low Power/voltage Cmos Sram 256k X 8 Bit

Manufacturer

Brillance Semiconductor

Datasheet

1.BS62LV2005SI.pdf (10 pages)

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R0201-BS62LV2005

• Wide Vcc operation voltage : 4.5V ~ 5.5V

• Very low power consumption :

• High speed access time :

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE2, CE1, and OE options

PRODUCT FAMILY

PIN CONFIGURATIONS

Brilliance Semiconductor Inc

FEATURES

BS62LV2005TC

BS62LV2005STC

BS62LV2005SC

BS62LV2005TI

BS62LV2005STI

BS62LV2005SI

Vcc = 5.0V

VCC

CE2

A11

A13

A15

A17

A16

A14

A12

-70

-55

PRODUCT

FAMILY

GND

DQ0

DQ1

DQ2

A17

A16

A14

A12

BSI

70ns(Max.) at Vcc = 5.0V

55ns(Max.) at Vcc = 5.0V

C-grade : 35mA (Max.) operating current

BS62LV2005TC

BS62LV2005STC

BS62LV2005TI

BS62LV2005STI

BS62LV2005SC

BS62LV2005SI

I- grade : 40mA (Max.) operating current

0.6uA (Typ.) CMOS standby current

-40

TEMPERATURE

OPERATING

Very Low Power/Voltage CMOS SRAM

256K X 8 bit

C to +70

C to +85

VCC

A15

CE2

A13

A11

A10

CE1

DQ7

DQ6

DQ5

DQ4

DQ3

A10

CE1

DQ7

DQ6

DQ5

DQ4

DQ3

GND

DQ2

DQ1

DQ0

. reserves the right to modify document contents without notice.

4.5V ~ 5.5V

RANGE

Vcc

Vcc=5.0V

SPEED

55 / 70

The BS62LV2005 is a high performance, very low power CMOS

Static Random Access Memory organized as 262,144 words by 8 bits

and operates from a wide range of 4.5V to 5.5V supply voltage.

Advanced CMOS technology and circuit techniques provide both high

speed and low power features with a typical CMOS standby current of

0.6uA and maximum access time of 55ns in 5V operation.

Easy memory expansion is provided by an active LOW chip

enable (CE1), an active HIGH chip enable (CE2), and active LOW

output enable (OE) and three-state output drivers.

The BS62LV2005 has an automatic power down feature, reducing the

power consumption significantly when chip is deselected.

The BS62LV2005 is available in the JEDEC standard 32 pin

450mil Plastic SOP, 8mmx13.4mm STSOP and 8mmx20mm TSOP.

(ns)

BLOCK DIAGRAM

DESCRIPTION

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CE1

CE2

A15

A16

A14

A12

Vdd

Gnd

A13

A17

Address

Buffer

Input

STANDBY

CCSB1

Vcc=5.0V

Control

25uA

6uA

POWER DISSIPATION

, Max)

Output

Buffer

Data

Input

Data

Decoder

Row

Operating

1024

Vcc=5.0V

35mA

40mA

BS62LV2005

A11

, Max)

Address Input Buffer

Column Decoder

Memory Array

A8 A3 A2 A1

Sense Amp

Write Driver

Column I/O

1024 x 2048

2048

256

TSOP - 32

STSOP - 32

SOP - 32

TSOP - 32

STSOP - 32

SOP - 32

Revision 2.4

April 2002

PKG TYPE

A10

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bs62lv2005si Summary of contents

Page 1

... A4 A17 1 32 VCC A16 2 31 A15 A14 3 30 CE2 A12 A13 BS62LV2005SC A4 8 BS62LV2005SI 25 A11 A10 CE1 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 DQ4 18 GND 16 17 ...

BSI PIN DESCRIPTIONS Name A0-A17 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input WE Write Enable Input OE Output Enable Input DQ0-DQ7 Data Input/Output Ports Vcc Gnd TRUTH TABLE MODE WE X Not selected (Power Down) ...

Page 3

BSI DC ELECTRICAL CHARACTERISTICS PARAMETER PARAMETER NAME Guaranteed Input Low V IL (2) Voltage Guaranteed Input High V IH (2) Voltage I Input Leakage Current IL I Output Leakage Current OL V Output Low Voltage OL V Output High Voltage ...

Page 4

BSI AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level AC TEST LOADS AND WAVEFORMS Ω 1928 5.0V OUTPUT 100PF INCLUDING Ω 1020 JIG AND SCOPE FIGURE 1A THEVENIN EQUIVALENT 667 OUTPUT ...

Page 5

BSI SWITCHING WAVEFORMS (READ CYCLE) (1,2,4) READ CYCLE1 ADDRESS D OUT (1,3,4) READ CYCLE2 CE1 CE2 D OUT (1,4) READ CYCLE3 ADDRESS OE CE1 CE2 D OUT NOTES high for read Cycle. 2. Device is continuously selected ...

Page 6

BSI AC ELECTRICAL CHARACTERISTICS WRITE CYCLE JEDEC PARAMETER PARAMETER NAME NAME t t AVAX E1LWH AVWL AVWH WLWH WHAX WR1 t t E2LAX WR2 t ...

Page 7

BSI (1,6) WRITE CYCLE2 ADDRESS CE1 CE2 WE D OUT D IN NOTES must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and ...

Page 8

BSI ORDERING INFORMATION BS62LV2005 PACKAGE DIMENSIONS STSOP - 32 R0201-BS62LV2005 BS62LV2005 SPEED 70: 70ns 55: 55ns GRADE + - + PACKAGE T: ...

Page 9

BSI PACKAGE DIMENSIONS (continued) PACKAGE DIMENSIONS (continued) TSOP - 32 SOP -32 R0201-BS62LV2005 b WITH PLATING BASE METAL SECTION A-A 9 BS62LV2005 Revision 2.4 April 2002 ...

Page 10

BSI REVISION HISTORY Revision Description 2.2 2001 Data Sheet release 2.3 Modify Standby Current (Typ. and Max.) 2.4 Modify some AC parameters. Modify 5V ICCSB1_Max(I-grade) from 10uA to 25uA. R0201-BS62LV2005 Date Apr. 15, 2001 Jun. 29, 2001 April,11,2002 10 BS62LV2005 ...

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