ht82v42 Holtek Semiconductor Inc., ht82v42 Datasheet - Page 18

• Manufacturer Part Number: ht82v42
• Description: Cis Analog Signal Processor
• Manufacturer: Holtek Semiconductor Inc.

Rev. 1.00
Auto-cycle Reset
Setup Register 4
Setup Register 5
Setup Register 6
Register
5~4
3~1
No.
Bit
0
1
3
0
4
7
LINEBYLINE
ACYCNRLC
RLCINT
INTM[1:0]
VSMPDET
VDEL[2:0]
POSNNEG
ClkMotr
Bit Name
POR
000
00
1
0
0
0
0
0
Writing to this register will cause the auto-cycle counter to be
reset to colour R. This function is only required when
LINEBYLINE=1. When this register is written, the reset func-
tion will be initiated immediately by an internal reset signal. If
the DCLK exists, the internal reset signal will keep active for
about 2 DCLK cycles. Otherwise, the device will keep in reset
state all the time.
Select line by line mode
0: normal operation
1: line by line operation
When LINEBYLINE=0, this bit has no effect
When LINEBYLINE=1, this bit controls the function of the
RLC/ACYC input signal and will control the multiplexer of the
offset/gain register.
0: RLC/ACYC pin enabled for Reset Level Clamp, internal se-
lection of input and offset/gain multiplexers.
1: Auto cycling enabled by pulsing the RLC/ACYC input pin.
This bit is used to determine whether the Reset Level
Clamping is used.
0: RLC disable
1: RLC enable
Colour selection bits used for internal modes.
00: Red
01: Green
10: Blue
11: Reserved
0: Normal operation, signal on the CDSCLK2 input pin is ap-
plied directly to the Timing Control Block
1: Programmable CDSCLK2 detect circuit is enabled. An in-
ternal synchronization pulse is generated from the signal
applied to the CDSCLK2 input pin and is applied to the Timing
Control Block.
When VSMPDEL=0, these bits have no effect.
When VSMPDEL=1, these bits set the programmable delay
from the detected edge of the signal on CDSCLK2. The inter-
nal generated pulse is delayed by VDEL DCLK periods from
the detected edge.
When VSMPDEL=0, this bit has no effect
When VSMPDEL=1, this bit controls whether positive or neg-
ative edges are detected.
0: Negative edge on the CDSCLK2 pin is detected and used to
generate an internal timing pulse
1: Positive edge on the CDSCLK2 pin is detected and used to
generate an internal timing pulse
Internal clock monitor.
0: normal active, OD[3:0] output ADC data.
1: internal clock test mode.
18
OD3
OD2
OD1
OD0
Pin
ClkMotr=0
OD3
OD2
OD1
OD0
Description
INTVSMP
Video sample clock
ADC clock
Reset sample clock
ClkMotr=1
November 20, 2009
HT82V42