ht82v42 Holtek Semiconductor Inc., ht82v42 Datasheet - Page 11

• Manufacturer Part Number: ht82v42
• Description: Cis Analog Signal Processor
• Manufacturer: Holtek Semiconductor Inc.

Input Sampling Block: Input Sampling and Referencing
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the input video.
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted instead.
If VRLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.
If VRLCEXT = 0, VVRLC is the output from the internal RLC DAC.
VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.
OFFSET DAC Block: OFFSET (BLACK - LEVEL) Adjust
The resultant signal V1 is added to the Offset DAC output.
PGA NODE: GAIN Adjust
The signal is then multiplied by the PGA gain,
ADC Block: Analogue-Digital Conversion
The analogue signal is then converted to a 16-bit unsigned number, with input range configured by PGAFS[1:0].
where the ADC full-scale range, VFS = 2.0V
Output Invert Block: Polarity Adjust
The polarity of the digital output may be inverted by control bit INVOP.
Output Formats
Latency of valid output data with respect to CDSCLK2 is
programmable by writing to control bits DEL[1:0]. The
latency for each mode is shown in the Operating Mode
Timing Diagrams section. Figure shows the output data
formats for Modes 1, 3 and 4. Figure shows the output
data formats for Mode 2. Table summarizes the output
data obtained for each format.
Rev. 1.00
V1 = VIN - VRESET...................................................................Eqn. 1
V1 = VIN - VVRLC .....................................................................Eqn. 2
VVRLC = (VRLCSTEP
V2 = V1 + { 315mV
V3 = V2
D1[15:0] = INT{ (V3 /VFS)
D1[15:0] = INT{ (V3 /VFS)
D1[15:0] = INT{ (V3 /VFS)
if D1[15:0] < 0
if D1[15:0] > 65535
D2[15:0] = D1[15:0]
D2[15:0] = 65535 - D1[15:0]
Output Data Formats (Mode 1, 3, 4)
[186 / (278 - PGA[7:0] ) ]...........................................Eqn. 5
(DAC[7:0] - 127.5) } / 127.5.....................Eqn. 4
D1[15:0] = 0
D1[15:0] = 65535
RLCV[3:0]) + VRLCBOT....................Eqn. 3
65535} + 32767
65535}
65535} + 65535
(INVOP = 0).....................................................Eqn. 9
(INVOP = 1)...................................................Eqn. 10
PGAFS[1:0] = 00 or 01 .................Eqn. 6
PGAFS[1:0] = 10 ..........................Eqn. 8
PGAFS[1:0] = 11 ..........................Eqn. 7
11
Output Format
4+4+4+4-Bit
(Nibble)
Output Data Formats (Mode 2)
Details of Output Data
Output Pins
OD3~OD0
November 20, 2009
A= d15~d12
B= d11~d8
C= d7~d4
D= d3~d0
HT82V42
Output