ht82v42 Holtek Semiconductor Inc., ht82v42 Datasheet - Page 17

• Manufacturer Part Number: ht82v42
• Description: Cis Analog Signal Processor
• Manufacturer: Holtek Semiconductor Inc.

Rev. 1.00
Setup Register 1
Setup Register 2
Setup Register 3
Software Reset
Register Map Description
Register
5~4
7~6
3~0
7~6
No.
Bit
5~
0
1
2
3
6
2
3
5
EN
CDS
Reserved
Reserved
PGAFS[1:0]
Mode3
INVOP
VRLCEXT
R L C D A C R N
G
DEL[1:0]
RLVC[3:0]
CDSREF[1:0]
Reserved
Bit Name
1111
POR
00
01
00
1
1
1
1
0
0
0
0
1
Setting this bit high, changes VRLC/VBIAS to Hi-Z, allowing
VRLC/VBIAS to be driven from an external power source.
0: Complete power down
1: fully active
Select correlated double sampling mode.
0: non-CDS mode
1: CDS mode
Default 1
Default 1
Adjust PGA output to optimize the ADC range for different po-
larity sensor output signals. Zero differential PGA input signal
gives.
00: Zero output (use for bipolar video)
01: Zero output
10: Full-scale positive output (use for negative going video)
11: Full-scale negative output (use for positive going video)
Mode3 setting
1: Mode3 enable
Digitally inverts the polarity of output data
0: negative going video gives negative going output
1: negative going video gives positive going output
Sets the output range of the RLCDAC.
0: RLCDAC ranges from 0 to AVDD.
1: RLCDAC ranges from 0 to VRT
Sets the output latency for the ADC clock periods.
1 ADC clock=2 DCLK periods. Under mode3, 1 ADC clock=3
DCLK periods.
00: Minimum latency
01: Delay by 1 ADC clock
10: Delay by 2 ADC clock
11: Delay by 3 ADC clock
Controls RLCDAC driving The VRLC pin defines the single
ended signal reference voltage or Reset Level Clamp Volt-
age. Refer to the Electrical Characteristic section for details.
Adjust reset timing under CDS mode
00: Advance 1 DCLK period
01: Normal
10: Retard 1 DCLK
11: Retard 2 DCLK
Reserved
Any write to this register will cause all functions to be reset. It
is recommended to execute a software reset after each power
on reset and before any other register writes. When this regis-
ter is written, the reset function will be initiated immediately by
an internal reset signal. If the DCLK exists, the internal reset
signal will keep active for about 2 DCLK cycles. Otherwise,
the device will keep in reset state all the time.
17
Description
November 20, 2009
HT82V42