ht82k70e-l Holtek Semiconductor Inc., ht82k70e-l Datasheet
ht82k70e-l
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ht82k70e-l Summary of contents
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... Application Note HA0075E MCU Reset and Oscillator Circuits Application Note Features Operating voltage: 1.8V~5.5V 43 bidirectional I/O lines 4K 16 Program Memory - HT82K70E Program Memory - HT82K76E-L 216 8 Data RAM One external interrupt input shared with I/O lines Two 16-bit programmable Timer/Event Counters with overflow interrupt ...
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... Block Diagram Pin Assignment Rev. 1.00 HT82K70E-L/HT82K76E-L 2 September 15, 2009 ...
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... VDD Note: Each pin can be chosen via configuration option to have a wake-up function. Rev. 1.00 HT82K70E-L/HT82K76E-L Description Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or input. Configuration options determine if the pins have pull-high resistors ...
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... V Input Low Voltage (RES) IL2 V Input High Voltage (RES) IH2 I I/O Port Sink Current OL I I/O Port Source Current OH R Pull-high Resistance PH Rev. 1.00 HT82K70E-L/HT82K76E-L +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Total............................................................ 100mA OH Test Conditions Min. V Conditions DD f =4MHz 1 ...
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... Parameter I Operating Current POR VDD Rise Rate to Ensure RSR POR Power-on Reset Maximum V Start Voltage POR_MAX Ensure Power-on Reset t Power-on Reset Low Pulse Width POR Rev. 1.00 HT82K70E-L/HT82K76E-L Test Conditions Min. V Conditions DD 1.8V~5.5V 400 3.3V~5.5V 400 3V f /64 SYS 3V WDTS=1 1 Test Conditions Min. ...
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... The main system clock, derived from either a Crys- tal/Resonator or RC oscillator is subdivided into four in- ternally generated non-overlapping clocks, T1~T4. The Rev. 1.00 HT82K70E-L/HT82K76E-L Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions ...
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... Note: PC12~PC8: Current Program Counter bits #12~#0: Instruction code address bits For the HT82K70E-L, the Program Counter Bits is 12 bits wide, the b12 column in the table is not applicable For the HT82K76E-L, the Program Counter Bits is 13 bits wide, i.e. from b12 ~ b0 Rev. 1.00 HT82K70E-L/HT82K76E-L ...
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... Program Counter and also contains data, table informa- tion and interrupt entries. Table data, which can be Program Memory Structure Rev. 1.00 HT82K70E-L/HT82K76E-L setup in any location within the Program Memory, is ad- dressed by separate table pointer registers. Special Vectors Within the Program Memory, certain locations are re- served for special usage such as reset and interrupts ...
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... Note: PC12~PC8: Current Program Counter bits when Configuration option TBHP is disable @7~@0: Table Pointer TBLP bits For the HT82K70E-L, the table address location is 12 bits wide, i.e. from b11 ~ b0 For the HT82K76E-L, the table address location is 13 bits wide, i.e. from b12 ~ b0 Rev. 1.00 HT82K70E-L/HT82K76E-L ...
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... As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Rev. 1.00 HT82K70E-L/HT82K76E-L 10 September 15, 2009 ...
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... Data Memory. Rev. 1.00 HT82K70E-L/HT82K76E-L Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and ...
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... The important point to note here is that in the example shown above, no reference is made to specific Data Memory ad- dresses. Rev. 1.00 HT82K70E-L/HT82K76E-L rather to the memory location specified by their corre- sponding Memory Pointer, MP0 or MP1. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of 00H and writing to the registers indi- rectly will result in no operation ...
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... Once Configuration option TBHP is enabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and TBHP value. Rev. 1.00 HT82K70E-L/HT82K76E-L Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO) ...
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... SET [m].i and CLR [m].i instructions. The ability to change I/O pins from output to input and vice versa by Rev. 1.00 HT82K70E-L/HT82K76E-L manipulating specific bits of the I/O control registers dur- ing normal program operation is a useful feature of these devices. ...
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... I/O pin, however to do this, the external interrupt enable bits in the INTC0 register must be disabled. Rev. 1.00 HT82K70E-L/HT82K76E-L Generic Input/Output Structure External Timer 0 Clock Input The external timer pin TMR0 is pin-shared with the I/O pin PA2. To configure this pin to operate as timer input, the corresponding control bits in the timer control reg- ister must be correctly set ...
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... This device contains two count-up timers of 16-bit capacities. As each timer has three different operating modes, they can be configured Rev. 1.00 HT82K70E-L/HT82K76E-L to operate as a general timer, an external event counter pulse width measurement device. There are two types of registers related to the Timer/Event Counters ...
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... Rev. 1.00 HT82K70E-L/HT82K76E-L associated low byte buffer. After this has been done, the low byte timer register can be read in the normal way. Note that reading the low byte timer register will result in ...
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... Timer/Event Counter 0 Control Register Timer/Event Counter 1 Control Register Rev. 1.00 HT82K70E-L/HT82K76E-L 18 September 15, 2009 ...
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... Control Register Operating Mode Select Bits for the Event Counter Mode Rev. 1.00 HT82K70E-L/HT82K76E-L In this mode, the external timer pin, TMR0 or TMR1, is used as the Timer/Event Counter clock source, however it is not divided by the internal prescaler. After the other ...
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... Timer/Event Counter Interrupt Enable bit in the Inter- rupt Control Register, INTC0, is reset to zero. Pulse Width Measure Mode Timing Chart Rev. 1.00 HT82K70E-L/HT82K76E-L I/O Interfacing The Timer/Event Counter, when configured to run in the event counter or pulse width measurement mode, re- quires the use of an external pin for correct operation. ...
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... Timer/Event Counter 0 set tmr1c.4 ; start Timer/Event Counter 1 Rev. 1.00 HT82K70E-L/HT82K76E-L woken up from its Power-down condition. To prevent such a wake-up from occurring, the timer interrupt re- quest flag should first be set high before issuing the HALT instruction to enter the Power Down Mode. ...
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... Rev. 1.00 HT82K70E-L/HT82K76E-L The various interrupt enable bits, together with their as- sociated request flags, are shown in the accompanying diagram with their order of priority. Once an interrupt subroutine is serviced, all the other in- terrupts will be blocked, as the EMI bit will be cleared au- tomatically ...
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... Rev. 1.00 HT82K70E-L/HT82K76E-L Interrupt Structure INTC0 Register INTC1 Register 23 September 15, 2009 ...
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... For an SPI Interrupt to occur, the global interrupt enable bit, EMI, and the corresponding SPI interrupt enable bit, Rev. 1.00 HT82K70E-L/HT82K76E-L ESII, must be first set. The SBEN bit in the SBCR regis- ter must also be set. An actual SPI Interrupt will take place when one of the one SPI interrupt request flags, ...
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... RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period Rev. 1.00 HT82K70E-L/HT82K76E-L to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage ...
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... These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the WDT Time-out Reset during Normal Operation Timing Chart Rev. 1.00 HT82K70E-L/HT82K76E-L Power Down function or Watchdog Timer. The reset flags are shown in the table: TO PDF RESET Conditions 0 ...
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... Note: * means warm reset - not implemented u means unchanged x means unknown Rev. 1.00 HT82K70E-L/HT82K76E-L RES Reset (Normal Operation ...
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... The external capacitor shown on the diagram does not influence the frequency of os- cillation. Crystal/Ceramic Oscillator Rev. 1.00 HT82K70E-L/HT82K76E-L RC Oscillator More information regarding the oscillator is located in Application Note HA0075E on the Holtek website. Watchdog Timer Oscillator The WDT oscillator is a fully self-contained free running on-chip RC oscillator with a typical period requiring no external components ...
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... When a Port pin wake-up oc- curs, the program will resume execution at the instruc- tion following the HALT instruction. Rev. 1.00 HT82K70E-L/HT82K76E-L When a PA0/PA1 or PB0/PB1 wake up occurs, bits in the WSR register can be read to know which pin changed first. If the system is woken interrupt, then two possi- ble situations may occur ...
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... It is important to realise that as there are no independent internal registers or configuration options associated with the length of the Watchdog Rev. 1.00 HT82K70E-L/HT82K76E-L Timer time-out completely dependent upon the fre- quency the internal WDT oscillator. Under normal program operation, a WDT time-out will initialise a device reset and set the status bit TO ...
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... WDTEN 1: enable 0: disable To selected Timer 1 source 1: WDT OSC 1 TMR1S SYS Where WDT OSC is selected as TMR1 source. WDT OSC is always enabled. 0 Unimplemented, read as 0 Rev. 1.00 HT82K70E-L/HT82K76E-L Description Wake-up Status Register - WSR Description according LVD_sel voltage Control Register - CTLR 31 September 15, 2009 ...
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... CPOL: I/O = clock polarity rising/falling edge: WSR register bit 0 If clock polarity set to rising edge (SPI_CPOL=1), serial clock timing follow SCK, otherwise (SPI_CPOL=0) SCK is the serial clock timing. Rev. 1.00 HT82K70E-L/HT82K76E-L Registers There are three registers associated with the SPI Inter- face. These are the SBCR register which is the control ...
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... Rev. 1.00 HT82K70E-L/HT82K76E-L SPI Bus Timing 33 September 15, 2009 ...
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... SDI will be shifted in. To Disable the SPI bus SCK, SDI, SDO, SCS should be floating. Rev. 1.00 HT82K70E-L/HT82K76E-L Operation All communication is carried out using the 4-line inter- face for both Master or Slave Mode. The timing diagram shows the basic operation of the bus. ...
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... Note: X: don t care (Z) floating Rev. 1.00 HT82K70E-L/HT82K76E-L Step 2. Setup the M0 and M1 bits select the Slave Mode. The CKS bit is don t care. Step 3. Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this must be same as the Master device. ...
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... The overall function of the WCOL bit can be disabled or enabled by a configuration option. Rev. 1.00 HT82K70E-L/HT82K76E-L Programming Considerations When the device is placed into the Power Down Mode note that data reception and transmission will continue. The TRF bit is used to generate an interrupt when the data has been transferred or received ...
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... Output slew rate select: 0ns, 50ns, 100ns or 200ns 10 PA, NMOS or CMOS by bit 11 TBHP: enable or disable Oscillator Options 12 OSC type selection crystal Watchdog Options 13 CLRWDT instructions: one or two instructions 14 WDT Clock Source WDT oscillator sys Rev. 1.00 HT82K70E-L/HT82K76E-L Options 37 September 15, 2009 ...
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... Application Circuits Rev. 1.00 HT82K70E-L/HT82K76E-L 38 September 15, 2009 ...
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... Care must be taken to en- Rev. 1.00 HT82K70E-L/HT82K76E-L sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for sub- traction. The increment and decrement instructions ...
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... DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev. 1.00 HT82K70E-L/HT82K76E-L Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 HT82K70E-L/HT82K76E-L Description 41 Cycles Flag Affected ...
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... ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.00 HT82K70E-L/HT82K76E-L 42 September 15, 2009 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.00 HT82K70E-L/HT82K76E-L addr 43 September 15, 2009 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1.00 HT82K70E-L/HT82K76E September 15, 2009 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.00 HT82K70E-L/HT82K76E-L addr 45 September 15, 2009 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.00 HT82K70E-L/HT82K76E-L Stack Stack Stack [m]. 0~6) 46 September 15, 2009 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.00 HT82K70E-L/HT82K76E-L [m]. 0~6) 47 September 15, 2009 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.00 HT82K70E-L/HT82K76E-L [ September 15, 2009 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.00 HT82K70E-L/HT82K76E-L 0 [m] [ September 15, 2009 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.00 HT82K70E-L/HT82K76E-L [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 50 September 15, 2009 ...
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... Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.00 HT82K70E-L/HT82K76E-L 51 September 15, 2009 ...
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... Package Information 28-pin SSOP (150mil) Outline Dimensions Symbol Rev. 1.00 HT82K70E-L/HT82K76E-L Dimensions in mil Min. Nom. 228 150 8 386 Max. 244 157 12 394 September 15, 2009 ...
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... SSOP (300mil) Outline Dimensions Symbol Rev. 1.00 HT82K70E-L/HT82K76E-L Dimensions in mil Min. Nom. 395 291 8 613 Max. 420 299 12 637 September 15, 2009 ...
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... SAW Type 32-pin (5mm´5mm) QFN Outline Dimensions Symbol Rev. 1.00 HT82K70E-L/HT82K76E-L Dimensions in mm. Min. Nom. 0.70 0.00 0.20 0.18 5.00 5.00 0.50 1.25 1.25 0.30 54 Max. 0.80 0.05 0.30 3.25 3.25 0.50 September 15, 2009 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 48W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 HT82K70E-L/HT82K76E-L Dimensions in mm 330.0 1.0 100.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 16.8 22.2 0.2 Dimensions in mm 330.0 1.0 100.0 0.1 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 32.2 38.2 0.2 55 September 15, 2009 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 HT82K70E-L/HT82K76E-L Dimensions in mm 16.0 0.3 8.0 0.1 1.75 0.1 7.5 0.1 +0.10/-0.00 1.55 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 6.5 0.1 10.3 0.1 2.1 0.1 0.30 0.05 13.3 0.1 56 September 15, 2009 ...
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... Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 HT82K70E-L/HT82K76E-L Dimensions in mm 32.0 0.3 16.0 0.1 1.75 0.10 14.2 0.1 2 Min. +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 12.0 0.1 16.2 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 0.1 57 September 15, 2009 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 HT82K70E-L/HT82K76E-L 58 September 15, 2009 ...