isppac20 Lattice Semiconductor Corp., isppac20 Datasheet - Page 14

• Manufacturer Part Number: isppac20
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

where V- and V+ are the voltages at the op amp inverting
and non-inverting inputs respectively. Because of feed-
back they are equal, so
and the differential output voltage V
V
Since the PACblock has two separate inputs (IA1 and
IA2) summed at the output amplifier input:
The input amplifiers have a programmable gain of
k·2 /V (g
The feedback amplifier transconductance g
2 /V, but may be disabled (g
output amplifier’s resistive feedback. The programmable
feedback capacitance lies in the range 1pF to 62pF.
The PACblock model from PAC-Designer is shown in
Figure 4. The output amplifier is configured as an invert-
ing mode op amp and illustrates the summing
configuration. The input instrument amplifiers are shown
to make it clear that unlike a typical inverting op amp, the
PACblock input impedance is extremely high. The input
amplifier (IA) transconductance (gain) is shown as the
value (k) above or below each amplifier. The gain of IA1
and IA2 are independently programmable. Because the
feedback transconductor IAF (designated here as R
can be disabled by the user, a user configurable switch
is shown in series.
Theory of Operation (Continued)
OUT+
-
V
V
IN
- V
-
V
IN
=
m1
g
IN
OUT-
m1
V
g
V
and g
IN
m1
g
OUT
m1
-
g
,
+
V
m1
V
+
V
OUT
m2
V
=
OUT
V
OUT
–
IN
OUT
k
) where k is an integer from -10 to 10.
V
1
g
g
OUT
m3
=
g
m
m3
g
V
g
g
m3
+
m
IN1
m3
g
+
(
3
m3
V
g
+
m3
(
+
+
+
m
V
OUT
(
+
k
1
V
sC
OUT
sC
= 0) to open-circuit the
2
OUT
(
2
2
g
V
-
F
F
m
OUT
OUT
+
–
V
+
–
(
IN2
sC
V
(
-
is the difference
V
+
sC
F
))
-
)
))
sC
m3
F
sC
)
F
is fixed at
F
(3a)
(3b)
(5a)
(5b)
(4)
F
)
14
Figure 4. PAC-Designer FilSum PACblock
The FilSum PACblock implements two primary functions:
the lossy integrator (low pass filter) and the integrator,
both with gain.
Lossy Integrator . The lossy integrator’s schematic within
PAC-Designer is shown in Figure 5. Manipulating the
PACblock transfer function of Equation 5 to better show
the pole frequency yields:
Figure 5. PAC-Designer PACblock Lossy Integrator
The DC gain of each input is set by k
the gain constant for the input amplifiers. Below the pole
frequency, this circuit can be viewed as a gain block.
Because of the bandwidth trim capacitance, there is a
minimum value of C
proximately 550kHz when the DC gain is one. For larger
gains, the input amplifier bandwidth begins to dominate
the overall PACblock response, limiting the bandwidth to
about 330kHz when the gain is 10.
Examining this transfer function shows the pole fre-
quency is (1/2 )(2g
options for feedback capacitance, there are at least 120
poles between 10kHz and 100kHz.
Two
Differential
Inputs
62pF, then 600kHz
PACblock
V
V
IN1
IN2
Specifications ispPAC20
2
2
IA1
IA2
IA1
IA2
V
k
k
k
k
OUT
1
2
1
2
Summation
m
Feedback Enable
=
F
/C). Since g
k
N
causing the bandwidth to be ap-
=–1, 2...10
k
f
P
1
V
IN1
1
10kHz. Due to the selection
+
+
sC
2
k
g
m
2
m
F
V
OA1
= 2 /V and 1pF
OA1
IN2
1
2.5V
C
R
2.5V
or k
C
F
F
R
F
F
2
1pF to 62pF
respectively,
Common-
Mode Voltage
Input
2
Differential
Output
V
OUT
(6)
C
F