isppac20 Lattice Semiconductor Corp., isppac20 Datasheet - Page 13

• Manufacturer Part Number: isppac20
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

sequence every time the device is turned on, or anytime
it is commanded externally via the CAL pin or by a JTAG
programming command. With this feature, the degrada-
tion of device offset performance that could occur over
time and temperature is dramatically reduced. Specifi-
cally, this means one PACblock of an ispPAC20 in a gain
configuration of one is guaranteed to never have an input
offset error greater than 1mV, after being auto-cali-
brated. For higher gain settings when offset is especially
important, the error is not multiplied by gain, but is instead
divided by it, due to the unique architecture of the
ispPAC20. When an individual PACblock is configured in
a gain of ten, that results in an input referred offset error
that never exceeds 100 V.
Internally, auto-calibration is accomplished by simulta-
neous successive approximation routines (SAR) to
determine the amount of offset error referred to each of
the two PACblock output amplifiers of the ispPAC20.
That error is then nulled by a calibration DAC for each
output amplifier. The calibration constant is not stored in
E
device is powered up or auto-cal is otherwise initiated.
Initiation of auto-cal occurs when an ispPAC20 is pow-
ered on as part of its normal power on routine, or by a
positive going pulse to the CAL pin, or by issuing the
appropriate JTAG command.
During auto-cal, all ispPAC20 OA PACell outputs are
driven to 0V and remain there until calibration is com-
plete. The timing for the calibration process is generated
internally. At power on, the sequence takes a maximum
of 250ms, and when auto-cal is initiated via the CAL pin
or by JTAG programming, it takes a maximum of 100ms
to complete. The longer time required at power on in-
sures the device power supply reaches its final value
before calibration begins. Additional attempts to initiate
auto-cal once calibration is in progress are ignored.
Finally, the only direct indication of auto-cal completion
will be the device’s OA outputs returning to operational
values from the 0V clamped state.
To insure maximum accuracy of the auto-cal procedure,
all digital signals to the ispPAC20 should be suspended
when calibration is in progress to avoid feed-through of
noise to critical analog circuitry. This is especially true
when auto-cal is initiated via JTAG command and the
programming port is in use. There is sufficient time,
however, to clock the JTAG controller back to its “reset”
state without affecting the calibration process.
Bandwidth Trim. The bandwidth of an OA PACell is
trimmed during manufacturing by adjusting the amplifier’s
Theory of Operation (Continued)
2
CMOS memory, but is recomputed each time the
13
feedback capacitance to optimize the step response. The
trimmed step response resembles that of a critically
damped system with minimum overshoot.
The bandwidth trim ensures a nominal feedback capaci-
tance is always present, limiting the small signal bandwidth
of an OA PACell to about 600kHz when configured in a
gain of 1 (G=1). This should not be confused with the
gain-bandwidth product of the op amp within the output
amplifier PACells which is approximately 5MHz. It is
important to note that the individual output amplifiers are
always in essentially the same fixed gain configuration
and do not, therefore, contribute to a decrease in signal
bandwidth at higher PACblock gain settings. Since the
gain of an individual PACblock is determined by varying
the g
direct proportion to gain, as it would be in a traditional
voltage feedback amplifier configuration. Specifically,
small signal bandwidth is only reduced by a factor of 2,
not the expected 10, with a PACblock gain setting change
of G=1 to G=10. This is a significant advantage of the
PACblock architecture.
Pole Accuracy Trim . Separate from the bandwidth trim
capacitance, each FilSum PACblock contains a range of
user selectable op amp feedback capacitance. This is
made possible by a parallel arrangement of seven ca-
pacitors, each in series with an E
user controls the position of the switches when selecting
from the available capacitor values. The resulting capaci-
tance is in parallel with the op amp feedback element,
IAF, making 128 possible pole locations available. The
capacitor values are not binarily weighted, instead they
are chosen to optimize and concentrate pole spacing
below 100kHz. There are 122 poles between 10kHz and
96kHz, which guarantees a step of no greater than 3.2%
anywhere in that frequency range (to the nearest com-
puted pole location). In fact, step size in over 50% of that
range is less than 1.0%. Finally, capacitors are trimmed
to achieve 5.0% accuracy (absolute) with regard to their
nominal value.
PACblock Transfer Function
The block diagram for a PACblock is shown in Figure 1.
The transfer function for a transconductor is:
Using KCL (Kirchoff’s current law) at the op amp inputs
and assuming the input is connected to IA1 only:
m
of the input amplifier, bandwidth is not reduced in
Specifications ispPAC20
I
I
P
M
=
=
-
g
g
m
m
·
·
V
V
IN
IN
2
CMOS switch. The
(1)
(2)