wm8350 Wolfson Microelectronics plc, wm8350 Datasheet - Page 224

• Manufacturer Part Number: wm8350
• Description: Wolfson Audioplus? Stereo Codec With Power Management
• Manufacturer: Wolfson Microelectronics plc

WM8350
REGISTER
Register 03h System Control 1
w
ADDRESS
11:10
BIT
9
7
6
5
4
3
1
0
CHIP_RESET_ENA
WDOG_DEBUG
CHIP_SET_UP
RSTB_TO[1:0]
MEM_VALID
BG_SLEEP
ON_DEB_T
IRQ_POL
LABEL
ON_POL
DEFAULT
11
0
0
0
0
0
0
1
1
1
1
0
Time that the /RST pin and /MEMRST output is
held low after the chip reaches the active state.
00 = 15ms
01 = 30ms
10 = 60ms
11 = 120ms
Default held in metal mask.
Bandgap sleep mode
0 = never in sleep mode
1 = sleep mode is controlled by Main SM
Default held in metal mask.
Halts watchdog timer for system debugging
0 = normal operation
1 = WDOG halt
Protected by security key.
[No description available]
Reset by state machine.
Indicates that the contents of external memory are
still valid.
This bit is cleared on startup and whenever
/MEMRST is asserted from the main state
machine. The system software should set this bit
once the external memory has been set up.
Controlled in hibernate mode by
MEMRST_HIB_MODE
0 = External memory is not valid and needs
restoring.
1 = External memory is valid.
Reset when /MEMRST is asserted.
A spare register bit that can be used by the system
to say if the chip has been configured. It is reset by
POR.
ON pin Shutdown function debounce time
0 = 10s
1 = 5s
Protected by security key.
ON pin polarity:
0 = Active high (ON)
1 = Active low (/ON)
Protected by security key. Reset by state machine.
Default held in metal mask.
IRQ pin polarity:
0 = Active low (/IRQ)
1 = Active high (IRQ)
Reset by state machine. Default held in metal
mask.
DESCRIPTION
PD, June 2009, Rev 4.1
REFER TO
Production Data
224