xr16m752im48 Exar Corporation, xr16m752im48 Datasheet - Page 4

no-image

xr16m752im48

Manufacturer Part Number
xr16m752im48
Description
Xr68m752 -high Performance Duart With 64-byte Fifo
Manufacturer
Exar Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
xr16m752im48-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
xr16m752im48-F
Manufacturer:
EAXR
Quantity:
20 000
Company:
Part Number:
xr16m752im48TR-F
Quantity:
1 410
Company:
Part Number:
xr16m752im48TR-F
Quantity:
1 440
XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
Pin Description
MODEM OR SERIAL I/O INTERFACE
RXRDYB#
TXRDYA#
RXRDYA#
TXRDYB#
RTSA#
(IRQ#)
N
INTA
INTB
(NC)
TXA
RXA
AME
32-QFN
P
22
21
23
IN
5
4
-
-
-
-
#
48-TQFP
P
30
29
43
31
18
33
IN
6
7
5
#
T
YPE
O
O
O
O
O
O
O
O
I
When 16/68# pin is HIGH for Intel bus interface, this output becomes
channel A interrupt output. The output state is defined by the user
through the software setting of MCR[3]. INTA is set to the active mode
and OP2A# output LOW when MCR[3] is set to a logic 1. INTA is set to
the three state mode and OP2A# to HIGH when MCR[3] is set to a logic
0. See MCR[3].
When 16/68# pin is LOW for Motorola bus interface, this output
becomes device interrupt output (active low, open drain). An external
pull-up resistor is required for proper operation.
When 16/68# pin is HIGH for Intel bus interface, this output becomes
channel B interrupt output. The output state is defined by the user
through the software setting of MCR[3]. INTB is set to the active mode
and OP2A# output to LOW when MCR[3] is set to a logic 1. INTA is set
to the three state mode and OP2A# to HIGH when MCR[3] is set to a
logic 0. See MCR[3].
When 16/68# pin is LOW for Motorola bus interface, this output is not
used.
UART channel A Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel A. See
used, leave it unconnected.
UART channel A Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel A. See
used, leave it unconnected.
UART channel B Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel B. See
used, leave it unconnected.
UART channel B Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel B. See
used, leave it unconnected.
UART channel A Transmit Data or infrared encoder data. Standard
transmit and receive interface is enabled when MCR[6] = 0. In this
mode, the TX signal will be HIGH during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In the
Infrared mode, the inactive state (no data) for the Infrared encoder/
decoder interface is LOW. If it is not used, leave it unconnected.
UART channel A Receive Data or infrared receive data. Normal receive
data input must idle HIGH. The infrared receiver pulses typically idles at
LOW but can be inverted by software control prior going in to the
decoder, see MCR[6]. If this pin is not used, tie it to VCC or pull it high
via a 100k ohm resistor.
UART channel A Request-to-Send (active low) or general purpose out-
put. This output must be asserted prior to using auto RTS flow control,
see EFR[6] and IER[6]. For auto RS485 half-duplex direction control,
see DLD[6].
4
D
ESCRIPTION
Table 3
Table 3
Table 3
Table 4
. If it is not
. If it is not
. If it is not
. If it is not
REV. 1.0.2

Related parts for xr16m752im48