xr16m752im48 Exar Corporation, xr16m752im48 Datasheet - Page 23

• Manufacturer Part Number: xr16m752im48
• Description: Xr68m752 -high Performance Duart With 64-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.2
A
.
A2-A0
DDRESS
1 1 0
1 1 1
1 1 1
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
T
ABLE
N
FIFO
RHR
MCR RD/WR
MSR
THR
FCR
LCR RD/WR Divisor
SPR RD/WR
TCR RD/WR Resume
R
LSR
TLR RD/WR RX Trig
Rdy
IER
ISR
AME
EG
8: INTERNAL REGISTERS DESCRIPTION.
RD/WR
R
W
WR
WR
RD
RD
RD
RD
RD
EAD
RITE
/
RX FIFO
RX FIFO
CTS Int.
Enabled
Enable
Trigger
Enable
FIFOs
Select
Global
Clock
Pres-
B
caler
Error
Input
Bit-7
Bit-7
CD#
Bit-7
Bit-3
Bit-3
IT
0/
0/
0
-7
RI# Input
RX FIFO
TCR and
RTS Int.
Enabled
Resume
RX Trig
ENable
Enable
Trigger
Set TX
THR &
FIFOs
Empty
Break
B
Bit-6
Bit-6
TSR
Bit-6
Bit-2
Bit-2
TLR
IT
0/
0/
0
-6
16C550 Compatible Registers
RX FIFO
TX FIFO
Resume
B Status
Set Par-
XonAny
Xoff Int.
RX Trig
Source
Enable
Trigger
Empty
DSR#
B
Input
Bit-5
Bit-5
Bit-5
THR
Bit-5
Bit-1
Bit-1
INT
ity
IT
0/
0/
0/
0/
-5
RX FIFO
TX FIFO
Lopback
Resume
A Status
Internal
Enable
Source
Trigger
Enable
RX Trig
Sleep
Parity
Break
CTS#
23
Mode
B
Even
Input
Bit-4
Bit-4
Bit-4
Bit-4
Bit-0
Bit-0
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
INT
RX
IT
0/
0/
0/
-4
S
INT Out-
Stat. Int.
Framing
HADED BITS ARE ENABLED WHEN
Modem
Source
TX Trig
Enable
Enable
Enable
Enable
OP2#/
Mode
Parity
B
Delta
DMA
Error
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
CD#
Halt
INT
put
RX
IT
0
-3
TX FIFO
Stat. Int.
RX Line
TX Trig
Enable
Source
Enable
(OP1#)
Reset
Parity
B
FIFO
Delta
Error
Bit-2
Bit-2
Bit-2
Stop
Bit-2
Bit-2
Bit-2
Rdy
Halt
INT
Bits
RI#
RX
IT
0
-2
TX FIFO
B Status
Source
Control
TX Trig
XR16M752/XR68M752
Enable
Length
Output
Empty
DSR#
Reset
RTS#
Over-
Word
B
FIFO
Error
Delta
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Halt
INT
RX
RX
run
TX
Int
IT
-1
TX FIFO
RX Data
RX Data
A Status
Enable
Source
Enable
Control
Length
Output
TX Trig
Ready
FIFOs
DTR#
CTS#
B
Word
Delta
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Halt
INT
EFR B
Int.
IT
-0
IT
See
See
See
See
See
-4=1
LCR ≠ 0xBF
C
LCR[7]=0
OMMENT
Table 13
Table 12
Table 13
Table 12
Table 12