lf3347 LOGIC Devices Incorporated, lf3347 Datasheet - Page 4

• Manufacturer Part Number: lf3347
• Description: High-speed Image Filter With Coefficient Ram
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
FUNCTIONAL DESCRIPTION
Coefficient Banks
The LF3347 has four coefficient banks
which feed coefficient values to the
multipliers. Each bank can store 256
12-bit coefficients. In the example
shown in Table 3, address 10 in coeffi-
cient banks 1 through 4 is loaded with
the following values: ABCH, 789H,
456H, 123H. The coefficient banks are
not written to until all four coefficients
have been loaded into the device.
A
sent to the multipliers. A value of 0 on
A
set 1 and so on.
Rounding/Offset
The accumulator output may be rounded
before being sent to the output select
section. Rounding is user-selectable and
is accomplished by adding the contents of
a round register to the accumulator
output (see Figure 2). There are sixteen
32-bit round registers. In the example in
Table 4, round register 10 is loaded with
76543210H. A round register is not
written to until all four data values have
been loaded into the device.
SELRND
register is used for rounding. A value of 0
on SELRND
value of 1 selects round register 1 and so
on. If rounding is not desired, a round
register should be loaded with 0 and
selected as the register for rounding.
Output Select
The filter output word width is 32-bits.
However, only 16-bits may be sent to the
device output. SHIFT4-0 determines
which 16 bits are passed to the device
output (See Table 1).
Output Limiting
An output limiting function is provided
for the output of the filter. When limiting is
enabled (LMTEN LOW), the limit register
selected with SELLMT
valid range of output values for the overall
filter. There are sixteen 32-bit limit
7-0
7-0
determines which coefficient set is
selects set 0. A value of 1 selects
3-0
determines which round
3-0
selects round register 0. A
3-0
determines the
registers. Each limit register contains both
an upper and lower limit value. The
lower limit is stored in bits 15-0 and the
upper limit is stored in bits 31-16. If the
value fed to the limiting circuitry is less
than the lower limit, the lower limit is
passed to the device output. If the value
fed to the limiting circuitry is greater than
the upper limit, the upper limit is passed
to the device output. When loading limit
values into the device, the upper limit must
2nd Word
2nd Word
** This bit represents the MSB of the Round Register.
2nd Word
** This bit represents the MSB of Upper Limit Register.
T
T
T
3rd Word
4th Word
5th Word
3rd Word
4th Word
5th Word
3rd Word
4th Word
5th Word
1st Word
1st Word
1st Word
Address
Address
Address
* This bit represents the LSB of the Round Register.
* This bit represents the MSB of the Lower Limit Register.
Bank 1
Bank 2
Bank 3
Bank 4
ABLE
ABLE
ABLE
R = Reserved. Must be set to “0”.
R = Reserved. Must be set to “0”.
3. C
4. R
5. L
High-Speed Image Filter with Coefficient RAM
CC
CC
CC
R
R
R
R
R
R
R
R
0
1
0
0
0
1
1
11
11
11
IMIT
OEFFICIENT
OUND
CC
CC
CC
4
R
R
R
R
R
R
R
R
0
0
1
1
0
0
1
10
10
10
R
CC
CC
CC
EGISTER
R
R
R
R
R
R
R
R
R
0
1
1
0
0
0
0
EGISTER
9
9
9
CC
CC
CC
B
R
R
R
R
R
R
R
R
0
0
1
0
1
0
0
ANK
8
8
8
L
CC
CC
CC
OADING
L
**0
**0
*0
0
1
1
0
0
0
0
0
0
0
0
1
L
OADING
7
7
7
OADING
be greater than the lower limit. In the
example shown in Table 4, limit register
15 is loaded with a lower limit of 0123H
and an upper limit of 7FEDH. A limit
register is not written to until all four data
values have been loaded into the device.
SELLMT
register is used for limiting. A value of 0
on SELLMT
value of 1 selects limit register 1 and so on.
CC
CC
CC
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
6
6
6
F
Video Imaging Products
ORMAT
CC
CC
CC
F
0
1
0
0
1
0
0
1
0
1
0
1
0
1
1
F
ORMAT
3-0
5
5
5
ORMAT
determines which limit
3-0
CC
CC
CC
0
1
0
1
0
0
1
1
1
1
0
0
0
0
1
selects limit register 0. A
4
4
4
CC
CC
CC
1
1
1
0
0
1
0
0
0
0
1
0
0
1
1
3
3
3
08/16/2000–LDS.3347-G
CC
CC
CC
0
1
0
1
0
0
0
0
1
1
1
0
0
1
1
2
2
2
LF3347
CC
CC
CC
1
0
0
1
1
1
0
1
0
1
1
1
0
0
1
1
1
1
CC
CC
CC
*0
0
0
1
0
1
0
0
0
0
1
1
1
1
1
0
0
0