lms12jc40 LOGIC Devices Incorporated, lms12jc40 Datasheet

lms12jc40

Manufacturer Part Number

lms12jc40

Description

12-bit Cascadable Multiplier-summer

Manufacturer

LOGIC Devices Incorporated

Datasheet

1.LMS12JC40.pdf (9 pages)

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DEVICES INCORPORATED

FEATURES

LMS12 B

DEVICES INCORPORATED

12 x 12-bit Multiplier with

Pipelined 26-bit Output Summer

Summer has 26-bit Input Port Fully

Independent from Multiplier

Inputs

Cascadable to Form Video Rate FIR

Filter with 3-bit Headroom

A, B, and C Input Registers Sepa-

rately Enabled for Maximum

Flexibility

28 MHz Data Rate for FIR Filtering

Applications

High Speed, Low Power CMOS

Technology

84-pin PLCC, J-Lead

ENC

ENA

CLK

25-0

LOCK

A REGISTER

IAGRAM

11-0

EXTENDED

PRODUCT REGISTER

SIGN

B REGISTER

The LMS12 is a high-speed 12 x 12-bit

combinatorial multiplier integrated

with a 26-bit adder in a single 84-pin

package. It is an ideal building block

for the implementation of very high-

speed FIR filters for video, RADAR,

and other similar applications. The

LMS12 implements the general form

in implementing polynomial approxi-

mations to transcendental functions.

ARCHITECTURE

A block diagram of the LMS12 is

shown below. Its major features are

discussed individually in the follow-

ing paragraphs.

MULTIPLIER

The A

LMS12 are captured at the rising edge

of the clock in the 12-bit A and B input

registers, respectively. These registers

are independently enabled by the

DESCRIPTION

•

11-0

B) + C. As a result, it is also useful

12-bit Cascadable Multiplier-Summer

11-0

and B

11-0

inputs to the

12-bit Cascadable Multiplier-Summer

25-0

ENB

FTS

ENA and ENB inputs. The registered

input data are then applied to a

12 x 12-bit multiplier array, which

produces a 24-bit result. Both the

inputs and outputs of the multiplier

are in two’s complement format. The

multiplication result forms the input

to the 24-bit product register.

SUMMER

The C

26-bit two’s complement number

which is captured in the C register at

the rising edge of the clock. The C

ENC input. The summer is a 26-bit

adder which operates on the C

contents of the product register to

produce a 26-bit sum. This sum is

applied to the 26-bit S register.

OUTPUT

The FTS input is the feedthrough

control for the S register. When FTS is

asserted, the summer result is applied

directly to the S output port. When

FTS is deasserted, data from the S

effecting a one-cycle delay of the

summer result. The S output port can

be forced to a high-impedance state by

driving the OE control line high. FTS

would be asserted for conventional

FIR filter applications, however the

insertion of zero-coefficient filter taps

may be accomplished by negating

FTS. Negating FTS also allows

application of the same filter transfer

function to two interleaved datas-

treams with successive input and

output sample points occurring on

alternate clock cycles.

25-0

Multiplier-Summers

inputs to the LMS12 form a

LMS12

08/16/2000–LDS.S12-J

LMS12

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lms12jc40 Summary of contents

Page 1

DEVICES INCORPORATED DEVICES INCORPORATED FEATURES 12 x 12-bit Multiplier with Pipelined 26-bit Output Summer Summer has 26-bit Input Port Fully Independent from Multiplier Inputs Cascadable to Form Video Rate FIR Filter with 3-bit Headroom A, B, and C Input Registers ...

Page 2

DEVICES INCORPORATED IGURE LOW IAGRAM FOR x(n) x( –1 Z APPLICATIONS The LMS12 is designed specifically for high-speed FIR filtering applications requiring a throughput rate of one output sample per clock period. ...

Page 3

DEVICES INCORPORATED ABLE IMING XAMPLE FOR CLK Cycle (n) n n+1 A Register Sum 4 A Register Sum 3 A Register Sum ...

Page 4

DEVICES INCORPORATED M R Above which useful life may be impaired (Notes AXIMUM ATINGS Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C V supply voltage with respect to ground ............................................................................ –0.5 ...

Page 5

DEVICES INCORPORATED SWITCHING CHARACTERISTICS OMMERCIAL PERATING ANGE Symbol Parameter t Clock Period CP t Clock Pulse Width Data Setup Time SAB t C Data Setup Time SC t ENA, ENB, ENC Setup Time ...

Page 6

DEVICES INCORPORATED SWITCHING CHARACTERISTICS (–55°C to +125°C) ILITARY PERATING ANGE Symbol Parameter t Clock Period CP t Clock Pulse Width Data Setup Time SAB t C Data Setup Time SC t ENA, ENB, ...

Page 7

DEVICES INCORPORATED NOTES 1. Maximum Ratings indicate stress specifications only. Functional oper- ation of these products at values beyond those indicated in the Operating Condi- tions table is not implied. Exposure to maximum rating conditions for ex- tended periods may ...

Page 8

... Top 22 View Plastic J-Lead Chip Carrier (J3) S CREENING LMS12JC40 LMS12JC35 GND ...

Page 9

DEVICES INCORPORATED ORDERING INFORMATION ...

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