lf3312 LOGIC Devices Incorporated, lf3312 Datasheet
lf3312
Related parts for lf3312
lf3312 Summary of contents
Page 1
... Synchronous Shift Register (Dual-channel) • FIFO + shift register; Channel B Synchronized to Channel A • Shift register + FIFO; One channel Synchronized to the other NOTE: This Preliminary Datasheet references LF3312BGC Engineering Samples with an ES marking under the part designation. Applications DTV/HDTV Video Stream Buffer Frame Synchronization ...
Page 2
... A user requiring more storage can cascade up to sixteen LF3312s into a larger array. A great deal of memory addressing flexibility is offered with the LF3312. In addition to simple clearing of the Write and Read pointers, either pointer may be set/jumped to any location within the entire address space. ...
Page 3
... SCL MEMORY CELL ARRAY B 12 518,400 x 12-bit BIN 11-0 622,080 x 10-bit 777,600 x 8-bit BWCLK BWCLK WRITE CONTROL B BCLR BSET BMARK BMARK 3 LF3312 12-Mbit Frame Buffer / FIFO Preliminary Datasheet RCLK READ AREN RSET CONTROL A RCLR AOE 12 AOUT 11-0 FLAG APF GENERATOR A APE ACOLLIDE, BCOLLIDE ...
Page 4
... SCL ADDR[23:0] 4 12-Mbit Frame Buffer / FIFO Preliminary Datasheet MARK RCLK READ READ READ ADDRESS RSET CONTROL A CONTROL RCLR 12 FLAG GENERATOR RCLK READ READ ADDRESS CONTROL RSET RCLR OE 12 Q[11:0] 24 RADDRSEL WADDRSEL 24 Video Imaging Product August 8, 2006 LDS.3312 O LF3312 REN OE Q[11:0] PF COLLIDE PE REN ...
Page 5
... After it “fills,” the LF3312 continues writing and the oldest data gets written over. If the memory core “empties” (and neither the read nor write pointer have been set or cleared during run-time) the read pointer stops incrementing, and the device re-reads the last written sample until more data is written ...
Page 6
... DEVICES INCORPORATED Operating Modes Single-channel synchronous shift register mode (OPMODE = 0) In OPMODE 0, the LF3312 becomes a single channel shift register with programmable total latency clock cycles. Writes and reads occur simultaneously, hence synchronous operation OPMODE 0, the user provides a single clock for both the input and output clocks and specifies a desired input-to-output data path latency, (ALAT) via the control interface ...
Page 7
... ROW_LENGTH to 1716 decimal = 6B4 hex. Offset circuitry within the LF3312 permits the user to cascade several chips in parallel and to use them collectively as a single large memory with a seamless address space. Data are read out sequentially by rising edges of RCLK, under the control of AREN (read enable), RSET (read pointer force to constant), and RCLR (read pointer clear to 0) ...
Page 8
... Internally, the LF3312 has a 24bit address space. When cascading LF3312s, each device’s write and read pointers behave identically. The LF3312 was designed to be cascaded in parallel. That is, the inputs of each device are tied together. The input data word (the data word placed on the AIN input port common for all devices ...
Page 9
... In contrast, during a read operation, if there is no acknowledgement back from the master device, the LF3312 interprets this were the end of the data transmission, and leaves SDA high, allowing the master to generate its stop signal. ...
Page 10
... R/W bit this time HIGH signifying a read and wait for an acknowledge. The user must write to the LF3312 to select the appropriate initial target register. Otherwise the starting position of the read is uncertain. Once the LF3312 acknowledges, the next byte of data on SDA is the contents of the addressed register sent from the device. If the master acknowledges, the LF3312 will send the next higher register’ ...
Page 11
... Write Cycle - Normal Mode t CSU t CSPW t CSU t CSU Read Cycle - PRE held low t CSPW t CSU t CDLY Write Cycle - PRE held low t CSPW t CSU 11 LF3312 12-Mbit Frame Buffer / FIFO Preliminary Datasheet CHD CSU CSU CHD Video Imaging Product August 8, 2006 LDS.3312 O ...
Page 12
... All pins must be connected. Clocks AWCLK - Write Clock A Data present on AIN11-0 is written into the LF3312 on the rising edge of AWCLK when AWEN was LOW for the previous rising edge of AWCLK. BWCLK - Write Clock B In two-channel modes(OPMODES 4-7), data present on BIN11-0 is written into the LF3312 on the rising edge of BWCLK when BWEN is LOW ...
Page 13
... In one-channel modes, BSET determines whether ASET forces the write address pointer to ALAT (BSET = BOUT,BIN (BSET = 1). In OPMODES 4-7, this control takes effect only when BWEN is LOW. LOGIC Devices Incorporated 12-Mbit Frame Buffer / FIFO Preliminary Datasheet 13 LF3312 Video Imaging Product August 8, 2006 LDS.3312 O ...
Page 14
... BIEN is used to enable/disable writing into the memory core. A LOW on BIEN enables writing, while a HIGH on BIEN disables writing. The internal B write address pointer is incremented by BWEN regardless of the BIEN level. Unless writing into memory disabled, tie BIEN LOW LOGIC Devices Incorporated 12-Mbit Frame Buffer / FIFO Preliminary Datasheet 14 LF3312 Video Imaging Product August 8, 2006 LDS.3312 O ...
Page 15
... BREN by one cycle. Therefore when desiring not to read a sample, BREN must be brought high the cycle before. PROGRAM - Serial/Parallel Interface Selector When the user wishes to use the serial microprocessor to configure the LF3312, the PROGRAM pin must be set LOW, whereas she wishes to use the parallel interface, PROGRAM must be set HIGH. LOAD – Instruction Load Bringing asynchronous control LOAD LOW updates the working instruction latches to match the current contents of the instruction preload latches ...
Page 16
... TDO is the output data pin when using JTAG. TRSTB - JTAG reset TRSTB is used to reset all the registers and state machine fount the the JTAG module. LOGIC Devices Incorporated 12-Mbit Frame Buffer / FIFO Preliminary Datasheet 16 LF3312 Video Imaging Product August 8, 2006 LDS.3312 O ...
Page 17
... Frame Buffer / FIFO (0000: 24-bit linear map; see reg 7) (00000000: 24-bit linear map; see reg 6) (00000000: default = 0; see reg 9, a) (00000000: default = 0; see reg 8, a) (00000000: default = 0; see reg 8, 9) (00000000) (00000000) (00000000) 17 LF3312 Preliminary Datasheet Video Imaging Product August 8, 2006 LDS.3312 O ...
Page 18
... BCLR is falling edge triggered) (0: ASET is falling edge triggered) (0: ACLR is falling edge triggered) (00: BPE, BPF are part-empty, -full) (00: APE, APF are part-empty, -full) (0000: lowest-address chip in cascade sequence) (0000: single chip - no cascade of multiple chips) 18 LF3312 Preliminary Datasheet Video Imaging Product August 8, 2006 LDS.3312 O ...
Page 19
... OPMODES, bringing RSET LOW forces/jumps the read pointer to the address defined by BLATENCY. In dual-channel modes, BLATENCY impacts channel B exactly as ALATENCY impacts channel A. Total Channel B data latency = TBD + (BLATENCY clock cycles). LOGIC Devices Incorporated 12-Mbit Frame Buffer / FIFO Preliminary Datasheet -2 clock cycles LF3312 Video Imaging Product August 8, 2006 LDS.3312 O ...
Page 20
... Synchronous Shift Register 1 channel Random Access ------- RESERVED 1 channel Asynchronous FIFO 2 channel Synchronous Shift Register 2 channel FIFO, B slaved channel FIFO, A slaved channel Asynchronous FIFO (default) 20 12-Mbit Frame Buffer / FIFO Preliminary Datasheet xOUT[3:0] tristated xOUT[1:0] tristated Video Imaging Product August 8, 2006 LDS.3312 O LF3312 ...
Page 21
... F-bit in EAV force read pointer(s) to marked address(es) (dflt) force read pointer(s) as shown in following table: OPMODE BCLR Read Pointer Equals: 0-3 1 BIN/BOUT address 0-3 0 BLAT address 4-7 x Ch. A=ALAT, Ch. B=BLAT 21 LF3312 12-Mbit Frame Buffer / FIFO Preliminary Datasheet Video Imaging Product August 8, 2006 LDS.3312 O ...
Page 22
... The corresponding pin continuously overrides the memory address counter as long held LOW. Memory address incrementing resumes when the pin is returned HIGH. 22 LF3312 12-Mbit Frame Buffer / FIFO Preliminary Datasheet Video Imaging Product August 8, 2006 LDS.3312 O ...
Page 23
... AIN v (W) AOUT f (R) AOUT v (R) AIN f (W) AIN h (W) AOUT f (R) AOUT h (R) AIN v (W) AIN h (W) AOUT v (R) AOUT h (R) 23 LF3312 12-Mbit Frame Buffer / FIFO Preliminary Datasheet BCOLLIDE BCOLLIDE (R) BCOLLIDE (R) BIN h (W) BOUT h (R) BCOLLIDE (R) BCOLLIDE (R) BCOLLIDE (R) BCOLLIDE (R) BCOLLIDE (R) ...
Page 24
... R, W addresses, modulo 1,658,880 (a) Note limits regarding the number of possible chips, related to WIDTH control: 8bit data less LF3312s (WIDTH = 0x) 10bit data less LF3312s (WIDTH = 10) 12bit data less LF3312s (WIDTH = 11) 24 LF3312 12-Mbit Frame Buffer / FIFO ...
Page 25
... CCint f=74MHz, V =3.6V (Note 6) CCo V =3.6V CCo T = 25° MHz 25° MHz A 25 LF3312 12-Mbit Frame Buffer / FIFO Preliminary Datasheet –65°C to +150°C –0. 2.0V –0. 4.0V –0. 3. > 400 mA Supply Voltage 1.71V < Vcc < 1.89V 3.00V < Vcc < 3.60V Min Typ ...
Page 26
... Parallel Interface Control Output Delay CDLY t Parallel Interface Control Tristate delay CZ LOGIC Devices Incorporated 12-Mbit Frame Buffer / FIFO Preliminary Datasheet Min 13 LF3312 LF3312BGC - Max Max Min Video Imaging Product August 8, 2006 LDS.3312 O ...
Page 27
... NOTE: REN should be brought LOW 2 rising edges of RCLK prior to expecting valid data on Q LOGIC Devices Incorporated t t WES WEH (n+1) (n+3) (n+ WES WEH (n+1) (n+3) (n+4) t RES t REH (n) (n+ 12-Mbit Frame Buffer / FIFO Preliminary Datasheet (n+5) data not data not written written (n+7) (n+5) (n+ (n+2) (n+3) Video Imaging Product August 8, 2006 LDS.3312 O LF3312 ...
Page 28
... Address "A" on ADDR) for the contents of location dumped onto Q LOGIC Devices Incorporated RWH RWS (0) (1) 2 .... (n+1) (n+ 23–0 (n-1) (n) 28 12-Mbit Frame Buffer / FIFO Preliminary Datasheet RWH RWS (2) (A) (A+ (n+8) ( (n+13) (A) (A+1) Video Imaging Product August 8, 2006 LDS.3312 O LF3312 (1) ...
Page 29
... RSET can be brought LOW (edge "7") 7 rising edges of RCLK after the LOAD transition, jumping the read pointer to the address programmed into the RADDR register. LOGIC Devices Incorporated 23-0 t RWS (A) (A+1) (A+2) OPMODE[2:0]=001 t DIS RWS RWH 29 LF3312 12-Mbit Frame Buffer / FIFO Preliminary Datasheet (A+3) (A+4) t ENA HIGH IMPEDANCE RWH t t RWS RWH Video Imaging Product August 8, 2006 LDS.3312 O ...
Page 30
... Similar capacitors should be installed between device VCC and the tester common, and device ground and tester common. b. Ground and VCC supply planes must be brought directly to the device leads. LOGIC Devices Incorporated 2 30 LF3312 12-Mbit Frame Buffer / FIFO Preliminary Datasheet Video Imaging Product August 8, 2006 LDS.3312 O ...
Page 31
... IGURE HRESHOLD EVELS t t ENA DIS OE 1 Measured V with I = –10mA and I = 10mA Measured V with I = –10mA and I = 10mA Video Imaging Product August 8, 2006 LDS.3312 O LF3312 3.0V Vth Vth ...
Page 32
... K GND BIN GND BIN BIN PDATA BIN BIN VCCO BIN VCCO TCK BIN BIN BIN PDATA TMS TDI GND VCC 0 INT P PDATA TRST_b TDO VCCO GND 1 1.00 REF Video Imaging Product August 8, 2006 LDS.3312 O LF3312 ...
Page 33
... DEVICES INCORPORATED Document History Page LF3312 12M OCUMENT ITLE Rev. ECN NO. Issue Date J 03/29/05 K 04/07/05 L 04/08/05 M 08/18/05 N 09/14/05 O 08/08/06 LOGIC Devices Incorporated FIFO BIT RAME UFFER Description of Change Cycle time changed to 13.5ns for fast FIFO modes Fixed pg 17 PROGRAM pin reference. (PR=0 serial) (PR=1 parallel) Cycle time changed to 13 ...