lf3311 LOGIC Devices Incorporated, lf3311 Datasheet - Page 13

• Manufacturer Part Number: lf3311
• Description: Horizontal / Vertical Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LF Interface ™
Continued
LOGIC Devices Incorporated
Both HPAUSE and VPAUSE allow the user to effectively slow the rate of data loading through the LF
Interface™. When HPAUSE is HIGH, the LF Interface™ affecting the data used for the Horizontal Filter is
held until HPAUSE is returned to a LOW. When VPAUSE is HIGH, the LF Interface™ affecting the data
used for the Vertical Filter is held until VPAUSE is returned to a LOW. Figures 10 through 13 display the
effects of both HPAUSE and VPAUSE while loading coefficient and control data. Table 15 shows an example
of loading data into the coefficient banks. The following data values are written into address 10 of coefficient
banks 0 through 7: 210H, 543H, C76H, 9E3H, 701H, 832H, F20H, 143H. Table 16 shows an example of
loading data into a Configuration Register. Data value 003H is written into Configuration Table 15 shows
an example of loading data into the coefficient banks. The following data values are written into address
10 of coefficient banks 0 through 7: 210H, 543H, C76H, 9E3H, 701H, 832H, F20H, 143H. Table 16 shows
an example of loading data into a Configuration Register. Data value 003H is written into Configuration
Register 4. Table 17 shows an example of loading data into a round register. Data value 7683F4A2H is
written into horizontal round register 12. Table 18 shows an example of loading data into a select register.
Data value 00FH is loaded into horizontal select register 2. Table 19 shows an example of loading data into
vertical limit register 7. Data value 390H is loaded as the lower limit and 743H is loaded as the upper limit. It
takes 9S clock cycles to load S coefficient sets into the device. Therefore, it takes 2304 clock cycles to
load all 256 coefficient sets. Assuming an 83 MHz clock rate, all 256 coefficient sets can be updated in
28.8 µs, which is well within vertical blanking time. It takes 5S or 3S clock cycles to load S round or limit
registers respectively. Therefore, it takes 256 clock cycles to update all round and limit registers (both
horizontal and vertical). Assuming an 83 MHz clock rate, all horizontal and vertical Round/Limit registers
can be updated in 3.08 µs.
Functional Description
Figure 13. Round Register Loading Sequence with HPAUSE and VPAUSE
Figure 12. Round Register Loading Sequence with HPAUSE and VPAUSE
PAUSE
CF
CLK
11-0
PAUSE
LD
CF
CLK
11-0
W1: Limit Register loaded with new data on this rising clock edge.
LD
W1: Round Register loaded with new data on this rising clock edge.
ADDR
ADDR
1
1
DATA
DATA
13
1
1
Horizontal / Vertical Digital Image Filter
LIMIT REGISTER
ROUND REGISTER
DATA
DATA
2
2
DATA
DATA
Improved Performance
3
3
Video Imaging Products
DATA
DATA
4
4
9/19/05 LDS.3311-C
W1
W1
LF3311