lf3312 LOGIC Devices Incorporated, lf3312 Datasheet - Page 26

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lf3312

Manufacturer Part Number
lf3312
Description
12-mbit Frame Buffer / Fifo
Manufacturer
LOGIC Devices Incorporated
Datasheet
DEVICES INCORPORATED
LOGIC Devices Incorporated
Symbol
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Switching Characteristics
Commercial Operating Range (0°C to +70°C) Notes 9, 10 (ns)
CYC1
CYC2
PWH
PWL
DS
DH
WES
WEH
RES
REH
LDS
LDH
RWS
RWH
D
F
DIS
ENA
CSU
CHD
CSPW
CDLY
CZ
Parameter
Cycle Time 1 (AWCLK,BWCLK,RCLK) - FIFO / Sh. Reg Modes
Cycle Time 2 (AWCLK,BWCLK,RCLK) - Full-time Random Access
Clock Pulse Width High (AWCLK,BWCLK,RCLK)
Clock Pulse Width Low (AWCLK,BWCLK,RCLK)
Setup Time, Data Inputs (AIN,BIN)
Hold Time, Data Inputs (AIN,BIN)
Write Enable Setup Time (AWEN,BWEN)
Write Enable Hold Time (AWEN,BWEN)
Read Enable Setup Time (AREN,BREN)
Read Enable Hold Time (AREN,BREN)
Load Setup Time
Load Hold Time
R/W Set/Clr Setup Time (ACLR,BCLR,ASET,BSET,RSET,RCLR)
R/W Set/Clr Hold Time (ACLR,BCLR,ASET,BSET,RSET,RCLR)
Access Time
Write Clock to Programmable Flags (A/BPE,A/BPF,A/BOLLIDE)
Tri-state Output Disable Delay
Tri-state Output Enable Delay
Parallel Interface Control Setup Time for Reads/Writes
Parallel Interface Control Hold Time for Reads/Writes
Parallel Interface Control Strobe pulse width
Parallel Interface Control Output Delay
Parallel Interface Control Tristate delay
26
12-Mbit Frame Buffer / FIFO
Preliminary Datasheet
13.4
Min
18
20
5
5
5
1
5
1
5
1
5
1
5
1
5
1
Video Imaging Product
-
LF3312BGC
Max
10
10
10
7
7
8
August 8, 2006 LDS.3312 O
Min
LF3312
Max

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