a8292 Allegro MicroSystems, Inc., a8292 Datasheet - Page 19

• Manufacturer Part Number: a8292
• Description: Dual Lnb Supply And Control Voltage Regulator
• Manufacturer: Allegro MicroSystems, Inc.

A8292
permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.
I
DiSEqC™ is a trademark of Eutelsat S.A.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its
Copyright ©2005, 2007, Allegro MicroSystems, Inc.
2
C™ is a trademark of Philips Semiconductors.
29X
0.55
0.08
D
+0.20
–0.10
0.25
C
+0.05
–0.07
2
1
1
2
Dual LNB Supply and Control Voltage Regulator
28
28
A
For the latest version of this document, visit our website:
5.00 ±0.15
0.50
3.15
B
Package ET 28-Pin MLP/QFN
5.00 ±0.15
3.15
www.allegromicro.com
0.90 ±0.10
SEATING
PLANE
C
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
C Reference land pattern layout (reference IPC7351
D Coplanarity includes exposed thermal pad and terminals
For Reference Only
(reference JEDEC MO-220VHHD-1)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
identifier appearance at supplier discretion)
QFN50P500X500X100-29V1M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
1.15
1
C
28
PCB Layout Reference View
0.30
3.15
4.80
0.50
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
3.15
4.80
19