a8292 Allegro MicroSystems, Inc., a8292 Datasheet - Page 10

• Manufacturer Part Number: a8292
• Description: Dual Lnb Supply And Control Voltage Regulator
• Manufacturer: Allegro MicroSystems, Inc.

A8292
4. Stop Condition. Defined by a positive edge on the SDA line,
tion. If the Read/Write bit is high, the master reads the contents of
register 1, followed by register 2 if a further read is performed. If
the Read/Write bit is low, the master writes data to one of the four
Control registers. Note that multiple writes are not permitted. All
write operations must be preceded with the address.
ter to determine if the slave device is responding to its address and
data, and it is used by the slave when the master is reading data
back from the slave. When the A8292 decodes the 7-bit address
field as a valid address, it responds by pulling SDA low during the
ninth clock cycle.
low during the clock cycle that follows the data byte, in order to
indicate that the data has been successfully received. In both cas-
es, the master device must release the SDA line before the ninth
clock cycle, in order to allow this handshaking to occur.
while SCL is high. Except to indicate a Start or Stop condi-
tion, SDA must be stable while the clock is high. SDA can
only be changed while SCL is low. It is possible for the Start
or Stop condition to occur at any time during a data transfer.
The A8292 always responds by resetting the data transfer
sequence.
The Read/Write bit is used to determine the data transfer direc-
The Acknowledge bit has two functions. It is used by the mas-
During a data write from the master, the A8292 also pulls SDA
Figure 3. I
2
C™ Interface. Read sequences after interrupt request.
SDA
SCL
IRQ
Fault
Event
Start
Dual LNB Supply and Control Voltage Regulator
0
1
0
2
0
3
Address
1
4
0
5
Read after Interrupt
A1
6
A0
7
R
1
8
AK
9
same way as in the data write sequence, and then retains control
of the SDA line and send the data from register 1 to the master.
On completion of the eight data bits, the A8292 releases the SDA
line before the ninth clock cycle, in order to allow the master to
acknowledge the data. If the master holds the SDA line low dur-
ing this Acknowledge bit, the A8292 responds by sending the data
from register 2 to the master. Data bytes continue to be sent to the
master until the master releases the SDA line during the Acknowl-
edge bit. When this is detected, the A8292 stops sending data and
waits for a stop signal.
Interrupt Request
The A8292 also provides an interrupt request pin, IRQ, which is
an open-drain, active-low output. This output may be connected
to a common IRQ line with a suitable external pull-up and can
be used with other I
from the master controller.
recognizes a fault condition, or at power-on, when the main sup-
ply, V
operating conditions. It is only reset to inactive when the I
master addresses the A8292 with the Read/Write bit set (causing a
read). Fault conditions are indicated by the TSD, VUV, and OCP
bits, and are latched in the Status register. See the Status register
section for full description.
D7
During a data read, the A8292 acknowledges the address in the
The IRQ output becomes active when either the A8292 first
IN
D6
, and the internal logic supply, V
D5
Status Register 1
D4
D3
2
C™-compatible devices to request attention
D2
D1
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
D0
NAK
Reload
Status Register
Stop
REG
, reach the correct
2
C™
10