lm80cimtx-5 National Semiconductor Corporation, lm80cimtx-5 Datasheet - Page 25

• Manufacturer Part Number: lm80cimtx-5
• Description: Serial Interface Acpi-compatible Microprocessor System Hardware Monitor
• Manufacturer: National Semiconductor Corporation

Bit
0
1
2
3
4
5
6
7
Functional Description
12.7 Interrupt Mask Register 2 — Address 04h
Power on default
Hot Temperature
BTI
FAN1
FAN2
CI (Chassis
Intrusion)
OS bit
Hot Temperature
Interrupt mode
select
OS bit Interrupt
mode select
Name
<
7:0
>
= 0000 0000 binary
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/
Write
(Continued)
A one disables the corresponding interrupt status bit for INT interrupt.
A one disables the corresponding interrupt status bit for INT interrupt.
A one disables the corresponding interrupt status bit for INT interrupt.
A one disables the corresponding interrupt status bit for INT interrupt.
A one disables the corresponding interrupt status bit for INT interrupt.
A one disables the corresponding interrupt status bit for INT interrupt.
A zero selects the default interrupt mode which gives the user an interrupt if the
temperature goes above the hot limit. The interrupt will be cleared once the status
register is read, but it will again be generated when the next conversion has completed.
It will continue to do so until the temperature goes below the hysteresis limit.
A one selects the one time interrupt mode which only gives the user one interrupt when
it goes above the hot limit. The interrupt will be cleared once the status register is read.
Another interrupt will not be generated until the temperature goes below the hysteresis
limit. It will also be cleared if the status register is read. No more interrupts will be
generated until the temperature goes above the hot limit again. The corresponding bit
will be cleared in the status register every time it is read but may not set again when the
next conversion is done. (See in Section 7.0)
A zero selects the default interrupt mode which gives the user an interrupt if the
temperature goes above the hot limit. The interrupt will be cleared once the status
register is read, but it will again be generated when the next conversion has completed.
It will continue to do so until the temperature goes below the hysteresis limit.
A one selects the one time interrupt mode which only gives the user one interrupt when
it goes above the hot limit. The interrupt will be cleared once the status register is read.
Another interrupt will not be generated until the temperature goes below the hysteresis
limit. It will also be cleared if the status register is read. No more interrupts will be
generated until the temperature goes above the hot limit again. The corresponding bit
will be cleared in the status register every time it is read but may not set again when the
next conversion is done. (See Section in Section 7.0)
25
Description
www.national.com