ap1250cmp APEC, ap1250cmp Datasheet

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ap1250cmp

Manufacturer Part Number
ap1250cmp
Description
2a Sink/source Bus Termination Regulator
Manufacturer
APEC
Datasheet

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AP1250CMP
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2A Sink/Source Bus Termination Regulator
Description
The AP1250CMP is a simple, cost-effective and
high-speed linear regulator designed to generate
termination voltage in double data rate (DDR)
memory system to comply with the JEDEC SSTL_2
and SSTL_18 or other specific interfaces such as
HSTL,
requirements. The regulator is capable of actively
sinking or sourcing up to 2A while regulating an
output voltage to within 40mV. The output
termination voltage cab be tightly regulated to track
1/2V
the desired output voltage can be pro-grammed by
externally forcing the REFEN pin voltage.
The AP1250CMP also incorporates a high-speed
differential amplifier to provide ultra-fast response in
line/load transient. Other features include extremely
low initial offset voltage, excellent load regulation,
current limiting in bi-directions and on-chip thermal
shut-down protection.
The AP1250CMP are available in the ESOP-8
(Exposed Pad) surface mount packages.
Pin Configuration
Pin Description
V
GND
V
REFEN
V
Pin Name
IN
CNTL
OUT
DDQ
by two external voltage divider resistors or
SCSI-2
Advanced Power
Electronics Corp.
Power Input
Ground
Gate Drive Voltage
Reference Voltage input and Chip Enable
Output Voltage
and
SCSI-3
Pin function
etc.
devices
Features
Application
Block Diagram
Ideal for DDR-I, DDR-II and DDR-III V
Sink and Source 2A Continuous Current
Integrated Power MOSFETs
Generates Termination Voltage for SSTL_2, SSTL
_18, HSTL, SCSI-2 and SCSI-3 Interfaces.
High Accuracy Output Voltage at Full-Load
Output Adjustment by Two External Resistors
Low External Component Count
Shutdown for Suspend to RAM (STR) Functionality
with High-Impedance Output
Current Limiting Protection
On-Chip Thermal Protection
Available in ESOP-8 (Exposed Pad) Packages
V
RoHS Compliant and 100% Lead (Pb)-Free
IN
Desktop PCs, Notebooks, and Workstations
Graphics Card Memory Termination
Set Top Boxes, Digital TVs, Printers
Embedded Systems
Active Termination Buses
DDR-I, DDR-II and DDR-III Memory Systems
and V
CNTL
No Power Sequence Issue
AP1250CMP
TT
200801091
Applications
1

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