tmp89fh40 TOSHIBA Semiconductor CORPORATION, tmp89fh40 Datasheet - Page 92

• Manufacturer Part Number: tmp89fh40
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.3
Functions
RA000
5.3.5
5.3.6
5.3.7
source clock.
operation.
time of the 8-bit up counter and within the clear time.
detected through interrupts generated by watchdog timer interrupt request signals.
from malfunctions and deadlock.
value to the last read value.
the watchdog timer operation is disabled.
of the 8-bit up counter.
Clear the 8-bit up counter at a point after
half of its overflow time and within a period
of the overflow time minus 1 source clock
cycle.
Clear the 8-bit up counter at a point after
half of its overflow time and within a period
of the overflow time minus 1 source clock
cycle.
Writing the watchdog timer control codes
Reading the 8-bit up counter
Reading the watchdog timer status
The watchdog timer control codes are written into WDCDR.
By writing 0x4E (clear code) into WDCDR, the 8-bit up counter is cleared to "0" and continues counting the
When WDCTR<WDTEN> is "0", writing 0xB1 (disable code) into WDCDR disables the watchdog timer
To prevent the 8-bit up counter from overflowing, clear the 8-bit up counter in a period shorter than the overflow
By designing the program so that no overflow will occur, the program malfunctions and deadlock can be
By applying a reset to the microcomputer using watchdog timer reset request signals, the CPU can be restored
The counter value of the 8-bit up counter can be read by reading WDCNT.
The stoppage of the 8-bit up counter can be detected by reading WDCNT at random times and comparing the
The watchdog timer status can be read at WDST.
WDST<WDTST> is set to "1" when the watchdog timer operation is enabled, and it is cleared to "0" when
WDST<WINTST2> is set to "1" when a watchdog timer interrupt request signal occurs due to the overflow
Example: When WDCTR<WDTEN> is "0", set the watchdog timer detection time to 2
Note:If the overflow of the 8-bit up counter and writing of 0x4E (clear code) into WDCDR occur simultaneously,
2. When the watchdog timer reset request signal is selected (when WDCTR<WDTOUT> is "1")
8-bit up counter overflows.
the 8-bit up counter is cleared preferentially and the overflow detection is not executed.
Setting WDCTR<WDTOUT> to "1" causes a watchdog timer reset request signal to occur when the
This watchdog timer reset request signal resets the TMP89FH40 and starts the warm-up operation.
to half of the overflow time, and allow a watchdog timer reset request signal to occur if a malfunction is detected.
LD
LD
LD
(WDCTR), 0y00110011
(WDCDR), 0x4E
(WDCDR), 0x4E
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;WDTW←10, WDTT←01, WDTOUT←1
;Clear the 8-bit up counter
;Clear the 8-bit up counter
20
/fcgck [s], set the counter clear time
TMP89FH40