ncp3030a ON Semiconductor, ncp3030a Datasheet - Page 16

• Manufacturer Part Number: ncp3030a
• Description: Ncp3030a, Ncp3030b Synchronous Pwm Controller
• Manufacturer: ON Semiconductor

Inductor Selection
input and output requirements. Some example conditions
are listed below to assist in the process.
are LC filtered to produce a lower dc output voltage (V
The output voltage can be changed by modifying the on time
relative to the switching period (T) or switching frequency.
The ratio of high side switch on time to the switching period
is called duty cycle (D). Duty cycle can also be calculated
using V
and the High side switch voltage drop V
Table 1. DESIGN PARAMETERS
Input Voltage
Nominal Input Voltage
Output Voltage
Input ripple voltage
Output ripple voltage
Output current rating
Operating frequency
When selecting the inductor, it is important to know the
A buck converter produces input voltage (V
OUT
Design Parameter
, V
IN
, the low side switch voltage drop V
D +
T
(VOUT
T
ON
(VIN
F +
(* D +
18
16
14
12
10
RIPPLE
RIPPLE
(V
8
6
4
2
0
4.5
(I
(Fsw)
1
T
(V
(V
OUT
OUT
IN
IN
Voltage Ripple
Maximum Allowable Voltage
Maximum Boost Voltage
)
)
)
)
)
)
6.5
T
Figure 30. Boost Voltage at 80% Duty Cycle
OFF
T
HSD
Example Value
8.5
9 V to 16 V
.
2.4 MHz
IN
300 mV
50 mV
3.3 V
12 V
) pulses that
3 A
10.5
(eq. 3)
(eq. 4)
http://onsemi.com
12.5
OUT
LSD
).
Input Voltage (V)
14.5
,
Boost Voltage
16
16.5
simplifies the equations used for inductor selection. The
formula for this is given in Equation 6.
percentage of ripple current in the inductor lies between
10% and 40%. When using ceramic output capacitors the
ripple current can be greater thus a user might select a higher
ripple current, but when using electrolytic capacitors a lower
ripple current will result in lower output ripple. Now,
acceptable values of inductance for a design can be
calculated using Equation 7.
is shown in Figure 31.
The ratio of ripple current to maximum output current
The designer should employ a rule of thumb where the
The relationship between ra and L for this design example
18.5
D +
L +
+
20.5
³ 27.5% +
3 A @ 15% @ 2.4 MHz
I
V
OUT
IN
22.5
V
* V
@ ra @ F
V
OUT
OUT
ra +
24.5
3.3 V
HSD
) V
3.3 V
12 V
SW
26.5
) V
I
OUT
LSD
DI
@ ( 1 * D ) ³ 2.2 mH
LSD
[ D +
@ ( 1 * 27.5% )
V
V
OUT
IN
(eq. 5)
(eq. 6)
(eq. 7)