tea1752t NXP Semiconductors, tea1752t Datasheet - Page 9

• Manufacturer Part Number: tea1752t
• Description: Greenchip Iii Smps Control Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TEA1752T_LT
Product data sheet
7.1.4 Fast latch reset
7.1.5 OverTemperature Protection (OTP)
7.2.1 t
7.2.2 Valley switching and demagnetization (PFCAUX pin)
7.2 Power Factor Correction circuit (PFC)
At initial start-up the switching is inhibited until the capacitor on the LATCH pin is charged
above 1.35 V (typical). No internal filtering is carried out on this pin. An internal zener
clamp of 2.9 V (typical) protects this pin from excessive voltages.
In a typical application the mains supply can be interrupted briefly to reset the latched
protection. The PFC bus capacitor, C
protection to reset.
Typically the PFC bus capacitor, C
level. When the latched protection is set, the VINSENSE clamping circuit is disabled. See
Section
to 0.87 V (typical), the latched protection is reset.
The latched protection is also reset by removing the voltage on pins V
Integrated overtemperature protection ensures the IC stops switching if the junction
temperature exceeds the thermal temperature shutdown limit.
Capacitor C
is supplied from the HV pin if the V
OTP is a latched protection that can be reset either by removing the voltage on pins V
and HV or by the fast latch reset function. See
The power factor correction circuit operates in quasi-resonant or discontinuous
conduction mode with valley switching. The next primary stroke only starts when the
previous secondary stroke has ended and the voltage across the PFC MOSFET has
reached a minimum value. The voltage on the PFCAUX pin is used to detect transformer
demagnetization and the minimum voltage across the external PFC MOSFET switch.
The power factor correction circuit is operated in t
reduction of a typical application is well within the class-D requirements.
The PFC MOSFET is switched on after the transformer has been demagnetized. Internal
circuitry connected to the PFCAUX pin detects the end of the secondary stroke. It also
detects the voltage across the PFC MOSFET. The next stroke is started when the voltage
across the PFC MOSFET is at its minimum in order to reduce switching losses and
ElectroMagnetic Interference (EMI) (valley switching).
If no demagnetization signal is detected on the PFCAUX pin, the controller generates a
Zero Current Signal (ZCS), 50 μs (typical), after the last PFCGATE signal.
If no valley signal is detected on the PFCAUX pin, the controller generates a valley signal,
4 μs (typical), after demagnetization was detected.
on
control
7.2.10. When the VINSENSE voltage drops below 0.75 V (typical) then increases
VCC
All information provided in this document is subject to legal disclaimers.
will not recharge from the HV mains while OTP is active. The OTP circuit
Rev. 02 — 24 June 2010
bus
CC
bus
, must discharge for the V
supply voltage is insufficient.
, does not need to discharge for this latched
TEA1752T; TEA1752LT
Section
on
control. The resulting mains harmonic
7.1.4.
GreenChip III SMPS control IC
CC
to drop to this reset
CC
© NXP B.V. 2010. All rights reserved.
and HV.
9 of 34
CC