w83627ehf Winbond Electronics Corp America, w83627ehf Datasheet - Page 74

• Manufacturer Part Number: w83627ehf
• Description: W83627ehf/ef W83627ehg/eg Winbond Lpc I/o
• Manufacturer: Winbond Electronics Corp America

Bit 5: AUXFANIN0 output value if bit 4 sets to 0. Write 1, pin111(AUXFANIN0) always generates a
Bit 4: AUXFANIN0 Input Control. Set to 1, pin111(AUXFANIN) acts as FAN tachometer input, which is
Bit 3: CPUFANIN0 output value if bit 2 sets to 0. Write 1, pin112(CPUFANIN0) always generates a
Bit 2: CPUFANIN0 Input Control. Set to 1, pin112(CPUFANIN0) acts as FAN tachometer input, which
Bit 1: SYSFANIN output value if bit 0 sets to 0. Write 1, pin113(SYSFANIN) always generates a logic
Bit 0: SYSFANIN Input Control. Set to 1, pin113(SYSFANIN) acts as FAN tachometer input, which is
6.8.46 Register 50h ~ 5Fh Bank Select Register - Index 4Eh (Bank 0)
Register Location:
Power on Default Value:
Attribute:
Size:
Bit 7: HBACS - High byte access. Set to 1, access Index 4Fh high byte register.
Bit 6: Reserved. This bit should be set to 0.
Bit 5: BEEP output control for AUXFANIN1 if the monitor value exceed the limit value. Write 1, enable
Bit 4: BEEP output control for CPUFANIN1 if the monitor value exceed the limit value. Write 1, enable
Bit 3: Reserved. This bit should be set to 0.
Bit 2-0: Index ports 0x50~0x5F Bank select.
Set to 1, select Bank1.
logic high signal. Write 0, pin111 always generates a logic low signal. This bit is default 0.
default value. Set to 0, this pin111 acts as FAN control signal and the output value of FAN
control is set by this register bit 5.
is default value. Set to 0, this pin112 acts as FAN control signal and the output value of FAN
control is set by this register bit 3.
default value. Set to 0, this pin113 acts as FAN control signal and the output value of FAN
control is set by this register bit 1.
Set to 0, access Index 4Fh low byte register. (default 1)
BEEP output. Write 0, disable BEEP output, which is default value.
BEEP output. Write 0, disable BEEP output, which is default value.
logic high signal. Write 0, pin112 always generates a logic low signal. This bit is default 0.
high signal. Write 0, pin113 always generates a logic low signal. This bit is default 0.
Set to 2, select Bank2.
Set to 0, select Bank0.
7
6
4Eh
80h
Read/Write
8 bits
5
4
3
W83627EHF/EF, W83627EHG/EG
2
1
-68-
0
BANKSEL0
BANKSEL1
BANKSEL2
Reserved
EN_CPUFANIN1_BP
EN_AUXFANIN1_BP
Reserved
HBACS