hmp8117 Intersil Corporation, hmp8117 Datasheet - Page 44

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hmp8117

Manufacturer Part Number
hmp8117
Description
Ntsc/pal Video Decoder
Manufacturer
Intersil Corporation
Datasheet

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Electrical Specifications
NOTES:
42. Guaranteed by design or characterization.
43. Test performed with C
44. Since the HMP8117 does not generate the sample clock, any clock jitter present on the CLK2 input will directly translate to pixel jitter on the
GENLOCK PERFORMANCE
Horizontal Locking Time
Long-Term horizontal Sync
Lock Range
Number of Missing Horizontal Syncs
Before Lost Lock Declared
Number of Missing Vertical Syncs
Before Lost Lock Declared
Long-Term Color Subcarrier
Lock Range
Vertical Sample Alignment
output data. The Vertical Sample Alignment parameter specifies the spatial pixel alignment from one scan line to the next using a stable CLK2
source.
PARAMETER
L
= 40pF, I
44
V
OL
CC
= 4mA, I
= V
H
V
SYNC LOST
SYNC LOST
SYMBOL
AA
t
LOCK
= 5.0V, T
OH
= -4mA. Input reference level is 1.5V for all inputs. V
A
= +25°C (Continued)
Time from Initial Lock
Acquisition to an Error of
1 Pixel. (Note 42)
Range over specified pixel jitter is
maintained. Assumes line time changes
by amount indicated slowly between
over one field. (Note 42)
Programmable via register 04
(Note 42)
Range over color subcarrier locking
time and accuracy specifications are
maintained. Subcarrier frequency
changes by amount indicated slowly
over 24 hours. (Note 42)
(Notes 42, 44)
HMP8117
TEST CONDITION
H
1 or 12
1 or 3
MIN
IH
± -
2
= 3.0V, V
1 or 12
1 or 3
±200
TYP
1/8
IL
10
3
= 0V.
1 or 12
1 or 3
MAX
±400
5
April 19, 2007
HSYNCs
VSYNCs
UNITS
Fields
Pixel
FN4643.3
Hz
ns
%

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