hmp8117 Intersil Corporation, hmp8117 Datasheet - Page 22

• Manufacturer Part Number: hmp8117
• Description: Ntsc/pal Video Decoder
• Manufacturer: Intersil Corporation

Control Registers
R
Sub-Addresses: 40
Sub-Addresses: 07
ADDRESS
14
20
24
31
34
SUB-
0A
0B
0C
0E
1A
1B
1C
1D
1E
00
01
02
03
04
05
06
08
0F
10
12
15
16
17
18
19
1F
32
35
36
37
41
42
50
51
52
53
7F
11
H
H
H
H
H
/13
-23
-29
/30
/33
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Product ID
Input Format
Output Format
Output Control
Genlock Control
Analog Input Control
Color Processing
Luma Processing
Sliced VBI Data Enable
Sliced VBI Data Output
VBI Data Status
Video Status
Interrupt Mask
Interrupt Status
Raw VBI Control
Raw VBI Start Count
Raw VBI Stop Count MSB/LSB
Raw VBI Line Mask_7_0
Raw VBI Line Mask_15_8
Raw VBI Line Mask_18_16
Brightness
Contrast
Hue
Saturation
Color Gain Adjust
Video Gain Adjust
Sharpness
Host Control
Closed Caption Data Registers
WSS Data & CRC Registers
Start H_BLANK MSB/LSB
End H_BLANK
Start V_BLANK MSB/LSB
End V_BLANK
End HSYNC
HSYNC Detect Window
MV Control
Reserved
Programmable Fractional Gain
MV Stripe Gate
Reserved
AGC Hysteresis
Device Revision
H
H
, 43
, 09
CONTROL REGISTER
H
H
-4F
, 0D
H
H
are reserved. Reads from these registers may return non-zero values.
22
, 2A
H
-2F
H
, 38
H
-3F
TABLE 10. CONTROL REGISTER SUMMARY
H
and 54
16
DEFAULT
03
03
01
RESET/
VALUE
H
H
-7E
7A
FE
1F
7A
0C
19
00
00
09
10
52
04
00
00
00
00
00
00
00
H
00
00
80
00
80
40
80
10
00
80
00
H
12
30
20
26
00
14
02
00
01
H
or 17
/4A
/4A
/02
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
HMP8117
H
H
H
are unused. Reads from these registers return 00
H
VALUE
Table 3
Table 3
Table 3
Table 3
Table 3
USE
C0
F0
90
30
21
22
H
H
H
H
H
H
Returns last two digits of part number in hex format.
Defaults to auto-detect of input video standard.
Defaults to 16-bit YCbCr data format.
Set Bits 7-6 to enable data and timing outputs.
Defaults to 27MHz CLK2, Rectangular Pixel Mode
Defaults to input signal select = CVBS1.
Set bit 7 for Soft Reset. Set bit 6 for Power Down.
BLANK programming changes for each video standard.
(same as above)
(same as above)
(same as above)
(same as above)
A wider window tolerates poorly timed video sources.
Set bits 5-4 to 11
A slower PFG improves AGC stability.
Set bit 5 to “1” for optimum performance.
Larger hysteresis improves AGC stability.
Production baseline revision is 01
B
for optimum performance.
COMMENTS
H
. Writes are ignored.
H
.
April 19, 2007
FN4643.3