cyv15g0203tb Cypress Semiconductor Corporation., cyv15g0203tb Datasheet - Page 12

• Manufacturer Part Number: cyv15g0203tb
• Description: Independent Clock Dual Hotlink Ii Serializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02105 Rev. *B
CYV15G0203TB DC Electrical Characteristics
AC Test Loads and Waveforms
CYV15G0203TB AC Electrical Characteristics
V
I
I
CYV15G0203TB Transmitter LVTTL Switching Characteristics Over the Operating Range
f
t
t
t
t
t
t
t
f
t
t
CYV15G0203TB REFCLKx Switching Characteristics Over the Operating Range
f
t
Notes:
10. Maximum I
11. Typical I
12. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
13. The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.
14. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
15. The ratio of rise time to falling time must not vary by greater than 2:1.
16. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
17. All transmit AC timing parameters measured with 1 ns typical rise time and fall time.
CC
CC
TS
TXCLK
TXCLKH
TXCLKL
TXCLKR
TXCLKF
TXDS
TXDH
TOS
TXCLKO
TXCLKOD
REF
REFCLK
Parameter
Power Supply
ODIF
[10,11]
[10,11]
GND
Parameter
outputs unloaded.
a continuous alternating 01 pattern. The redundant outputs on each channel are powered down.
V
th
[14]
[14]
[14, 15, 16, 17]
[14, 15, 16, 17]
≤ 1 ns
= 1.4V
CC
CC
is measured under similar conditions except with V
R1 = 590Ω
R2 = 435Ω
C
(Includes fixture and
probe capacitance)
Output Differential Voltage
|(OUT+) − (OUT−)|
Max Power Supply Current
Typical Power Supply Current
L
is measured with V
(c) LVTTL Input Test Waveform
≤ 7 pF
(a) LVTTL Output Test Load
TXCLKx Clock Cycle Frequency
TXCLKx Period=1/f
TXCLKx HIGH Time
TXCLKx LOW Time
TXCLKx Rise Time
TXCLKx Fall Time
Transmit Data Set-up Time to TXCLKx↑ (TXCKSELx = 0)
Transmit Data Hold Time from TXCLKx↑ (TXCKSELx = 0)
TXCLKOx Clock Frequency = 1x or 2x REFCLKx Frequency
TXCLKOx Period = 1/f
TXCLKO Duty Cycle centered at 60% HIGH time
REFCLKx Clock Frequency
REFCLKx Period = 1/f
2.0V
0.8V
Description
CC
3.0V
C
L
= MAX, T
2.0V
0.8V
3.3V
TS
A
= 25°C, with both channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and
TOS
REF
R1
R2
[12]
V
[13]
Description
th
≤ 1 ns
CC
= 1.4V
= 3.3V, T
100Ω differential load
150Ω differential load
REFCLKx =
MAX
REFCLKx =
125 MHz
(continued)
A
= 25°C, with both channels enabled and one Serial Line Driver per channel sending
V
V
Test Conditions
IHE
ILE
≤ 270 ps
Commercial
Commercial
20%
(d) CML/LVPECL Input Test Waveform
(Includes fixture and
probe capacitance)
(b) CML Output Test Load
R
L
= 100Ω
80%
V
V
IHE
ILE
Min.
Typ.
450
560
435
425
Min.
19.5
6.66
19.5
6.66
–1.9
19.5
0.2
0.2
2.2
2.2
2.2
1.0
6.6
CYV15G0203TB
80%
R
L
[12]
Max.
1000
Max.
20%
51.28
51.28
51.28
Max.
900
530
520
≤ 270 ps
150
150
150
1.7
1.7
Page 12 of 19
0
MHz
MHz
MHz
Unit
Unit
mV
mV
mA
mA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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