cyv15g0203tb Cypress Semiconductor Corporation., cyv15g0203tb Datasheet

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cyv15g0203tb

Manufacturer Part Number
cyv15g0203tb
Description
Independent Clock Dual Hotlink Ii Serializer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-02105 Rev. *B
Features
• Second-generation HOTLink
• Compliant to SMPTE 292M and SMPTE 259M video
• Dual-channel video serializer
• Supports half-rate and full-rate clocking
• Internal phase-locked loops (PLLs) with no external
• Redundant differential PECL-compatible serial outputs
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Low-power 1.4W @ 3.3V typical
• Single 3.3V supply
• Thermally enhanced BGA
• Pb-Free package option available
• 0.25µ BiCMOS technology
standards
PLL components
per channel
— 195- to 1500-Mbps serial data signaling rate
— Simultaneous operation at different signaling rates
— No external bias resistors required
— Signaling-rate controlled edge-rates
— Internal source termination
10
10
CYV15G0203TB
Independent Clock Dual HOTLink II™ Serializer
Independent
Serializer
®
Channel
technology
Figure 1. HOTLink II™ System Connections
3901 North First Street
Reclocked
Reclocked
Output
Output
Serial Links
Functional Description
The CYV15G0203TB Independent Clock Dual HOTLink II™
Serializer is a point-to-point or point-to-multipoint communica-
tions building block enabling transfer of data over a variety of
high-speed serial links including SMPTE 292M and SMPTE
259M video applications. It supports signaling rates in the
range of 195 to 1500 Mbps per serial link. The two channels
are independent and can simultaneously operate at different
rates. Each channel accepts 10-bit parallel characters in an
Input Register and converts them to serial data. Figure 1 illus-
trates typical connections between independent video co-
processors and corresponding CYV15G0203TB Serializer
and CYV15G0204RB Reclocking Deserializer chips.
The CYV15G0203TB satisfies the SMPTE-259M and SMPTE-
292M compliance as per SMPTE EG34-1999 Pathological
Test Requirements.
As
CYV15G0203TB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data, and BIST) with other HOTLink
devices. Each channel of the CYV15G0203TB Dual HOTLink
II device accepts scrambled 10-bit transmission characters.
These characters are serialized and output from dual Positive
ECL (PECL) compatible differential transmission-line drivers
at a bit-rate of either 10- or 20-times the input reference clock
for that channel.
Each channel contains an independent BIST pattern
generator. This BIST hardware allows at-speed testing of the
high-speed serial data paths in each transmit section of this
device, each receive section of a connected HOTLink II
device, and across the interconnecting links.
The CYV15G0203TB is ideal for SMPTE applications where
different data rates and serial interface standards are
necessary for each channel. Some applications include multi-
format routers, switchers, format converters, and cameras.
a
second-generation
San Jose
Reclocking Deserializer
CYV15G0204RB
Independent
Channel
,
CA 95134
HOTLink
CYV15G0203TB
Revised July 11, 2005
10
10
408-943-2600
device,
the
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cyv15g0203tb Summary of contents

Page 1

... CYV15G0203TB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data, and BIST) with other HOTLink devices. Each channel of the CYV15G0203TB Dual HOTLink II device accepts scrambled 10-bit transmission characters. These characters are serialized and output from dual Positive ...

Page 2

... CYV15G0203TB Serializer Logic Block Diagram Document #: 38-02105 Rev. *B x10 x10 Phase Phase Align Align Buffer Buffer Serializer Serializer TX TX CYV15G0203TB Page [+] Feedback ...

Page 3

... Transmit PLL Transmit PLL OE[2..1]B Clock Multiplier B Clock Multiplier Character-Rate Clock B PABRSTB TXBISTB TXRATE[A..B] TXCKSEL[A..B] PABRST[A..B] TXBIST[A..B] OE[2..1][A..B] CYV15G0203TB = Internal Signal RESET OE[2..1]A OUTA1+ OUTA1– OUTA2+ OUTA2– OE[2..1]B OUTB1+ OUTB1– OUTB2+ OUTB2– = Internal Signal RESET TRST JTAG TMS Boundary ...

Page 4

... CLKB– DA[1] REF TX NC GND NC GND GND CLKB+ CLKOA ADDR ADDR TX NC GND NC GND [2] [1] ERRA GND NC GND CLKOB CLKA CYV15G0203TB OUT GND A2– OUT A2+ SPD TRST TDO ...

Page 5

... CLKB– [0] DA[ REF GND GND NC GND DA[3] CLKOA CLKB ADDR ADDR GND NC GND DA[2] ERRA [1] [ GND NC GND DA[0] CLKA CLKOB CYV15G0203TB OUT B1– OUT B1+ TMS TDI ...

Page 6

... Pin Definitions CYV15G0203TB Dual HOTLink II Serializer Name I/O Characteristics Transmit Path Data and Status Signals TXDA[9:0] LVTTL Input, TXDB[9:0] synchronous, sampled by the associated TXCLKx↑ or [2] REFCLKx↑ TXERRA LVTTL Output, TXERRB synchronous to [3] REFCLKx↑ , asynchronous to transmit channel enable / disable, asynchronous to loss or return of REFCLKx± ...

Page 7

... Pin Definitions (continued) CYV15G0203TB Dual HOTLink II Serializer Name I/O Characteristics [4] SPDSELA 3-Level Select SPDSELB static control input Device Configuration and Control Bus Signals WREN LVTTL input, asynchronous, internal pull-up ADDR[2:0] LVTTL input asynchronous, internal pull-up DATA[3:0] LVTTL input asynchronous, internal pull-up Internal Device Configuration Latches [6] TXCKSEL[A ...

Page 8

... TXCLKOx. Each clock multiplier PLL can accept a REFCLKx± input between 19.5 MHz and 150 MHz, however, this clock range is limited by the operating mode of the CYV15G0203TB clock multiplier (TXRATEx) and by the level on the associated SPDSELx input. SPDSELx are 3-level select operating ranges for the serial data outputs and inputs of the associated channel ...

Page 9

... Device Configuration and Control Interface The CYV15G0203TB is highly configurable via the configu- ration interface. The configuration interface allows each channel to be configured independently. Table 2 lists the configuration latches within the device including the initial- ization value of the latches upon the assertion of RESET ...

Page 10

... TXBISTB (111b) Document #: 38-02105 Rev. *B JTAG Support The CYV15G0203TB contains a JTAG port to allow system level diagnosis of device interconnect. Of the available JTAG modes, boundary scan, and bypass are supported. This capability is present only on the LVTTL inputs and outputs and the REFCLKx± clock input. The high-speed serial inputs and outputs are not part of the JTAG test chain ...

Page 11

... Document #: 38-02105 Rev. *B Static Discharge Voltage.......................................... > 2000 V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Power-up Requirements The CYV15G0203TB requires one power-supply. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Operating Range + 0.5V Range ...

Page 12

... LVTTL Output Test Load 3.0V 2.0V 2. 1.4V th 0.8V 0.8V GND ≤ (c) LVTTL Input Test Waveform CYV15G0203TB AC Electrical Characteristics Parameter CYV15G0203TB Transmitter LVTTL Switching Characteristics Over the Operating Range f TXCLKx Clock Cycle Frequency TS t TXCLKx Period=1/f TXCLK TS [14] t TXCLKx HIGH Time TXCLKH [14] t TXCLKx LOW Time ...

Page 13

... JTAG Test Clock Period TCLK CYV15G0203TB Device RESET Characteristics Over the Operating Range t Device RESET Pulse Width RST CYV15G0203TB Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range Parameter t Bit Time B [14] t CML Output Rise Time 20−80% (CML Test Load) ...

Page 14

... Capacitance Parameter Description C TTL Input Capacitance INTTL C PECL input Capacitance INPECL CYV15G0203TB HOTLink II Transmitter Switching Waveforms Transmit Interface t Write Timing TXCLKH TXCLKx selected TXCLKx TXDx[9:0] Transmit Interface Write Timing REFCLKx selected t REFH TXRATEx = 0 REFCLKx TXDx[9:0] Transmit Interface Write Timing REFCLKx selected ...

Page 15

... CYV15G0203TB HOTLink II Transmitter Switching Waveforms Transmit Interface TXCLKOx Timing t TXRATEx = 0 REFCLKx Note 22 TXCLKOx CYV15G0203TB HOTLink II Bus Configuration Switching Waveforms Bus Configuration Write Timing ADDR[2:0] DATA[3:0] WREN Document #: 38-02105 Rev REFCLK t REFH REFL Note TXCLKO TXCLKO t WRENP t DATAS CYV15G0203TB (continued) ...

Page 16

... VCC POWER E04 VCC POWER E17 VCC POWER E18 VCC POWER E19 VCC POWER E20 VCC POWER F01 NC NO CONNECT CYV15G0203TB Ball ID Signal Name Signal Type F17 NC NO CONNECT F18 NC NO CONNECT F19 NC NO CONNECT F20 NC NO CONNECT G01 GND GROUND ...

Page 17

... VCC POWER V17 NC NO CONNECT V18 NC NO CONNECT V19 NC NO CONNECT V20 NC NO CONNECT W01 TXDB[5] LVTTL IN W02 TXDB[7] LVTTL IN CYV15G0203TB Ball ID Signal Name Signal Type L20 GND GROUND M01 NC NO CONNECT M02 NC NO CONNECT W03 NC NO CONNECT W04 NC NO CONNECT ...

Page 18

... Cypress against all charges. Package Name Package Type BL256 256-Ball Thermally Enhanced Ball Grid Array BL256 Pb-Free 256-Ball Thermally Enhanced Ball Grid Array CYV15G0203TB Operating Range Commercial Commercial 51-85123-*E Page [+] Feedback ...

Page 19

... Document History Page Document Title: CYV15G0203TB Independent Clock Dual HOTLink II™ Serializer Document Number: 38-02105 ISSUE REV. ECN NO. DATE ** 246850 See ECN *A 338721 See ECN *B 384307 See ECN Document #: 38-02105 Rev. *B ORIG. OF CHANGE DESCRIPTION OF CHANGE FRE New Data Sheet SUA Added Pb-Free package option availability ...

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