adau1373 Analog Devices, Inc., adau1373 Datasheet - Page 73

• Manufacturer Part Number: adau1373
• Description: Low Power Codec With Speaker And Headphone Amplifier Adau1373
• Manufacturer: Analog Devices, Inc.

REGISTER MAP SUMMARY (DEFAULT)
Table 34 is the summary of the control registers for the ADAU1373
in default mode using an MDRC, which can be accessed using
an I
Table 34. Register Summary
Reg Name
00
01
02
03
04
05
06
07
08
09
0A RLINE1_OUT
0B
0C RLINE2_OUT
0D LCD_OUT
0E
0F
10
11
12
13
14
15
16
17
18
19
1A LHPMIX
1B
1C EPMIX
1D HP_CTRL
1E
1F
21
22
23
24
25
26
27
28
29
2A PLLA_CTRL2
2B
2C PLLA_CTRL4
2D PLLA_CTRL5
2E
2F
30
31
32
33
34
35
36
37
INPUT_MODE
AIN1L_CTRL
AIN1R_CTRL
AIN2L_CTRL
AIN2R_CTRL
AIN3L_CTRL
AIN3R_CTRL
AIN4L_CTRL
AIN4R_CTRL
LLINE1_OUT
LLINE2_OUT
RCD_OUT
LHP_OUT
RHP_OUT
ADC_GAIN
LADC_MIXER
RADC_MIXER
LLINE1MIX
RLINE1MIX
LLINE2MIX
RLINE2MIX
LCDMIX
RCDMIX
RHPMIX
HP_CTRL2
LS_CTRL
EPCONTROL
MICBIAS_CTRL1 [7:0] VBATLOW
MICBIAS_CTRL2 [7:0] RESERVED
OUTPUT_
CONTROL
PWDN_CTRL1
PWDN_CTRL2
PWDN_CTRL3
DPLLA_CTRL
PLLA_CTRL1
PLLA_CTRL3
PLLA_CTRL6
DPLLB_CTRL
PLLB_CTRL1
PLLB_CTRL2
PLLB_CTRL3
PLLB_CTRL4
PLLB_CTRL5
PLLB_CTRL6
HEADDECT
ADC_DAC_
STATUS
2
C port. Register 0x80 to Register 0xBD are shared with the
Bits
[7:0] GAINMODE3
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0] ADCRGAIN3
[7:0]
[7:0]
[7:0] LLINE1MIX7
[7:0] RLINE1MIX7
[7:0] LLINE2MIX7
[7:0] RLINE2MIX7
[7:0] CDLMIX7
[7:0] CDRMIX7
[7:0] LHPMIX7
[7:0] RHPMIX7
[7:0] EPMIX7
[7:0]
[7:0] RESERVED
[7:0] CDDRIVE
[7:0]
[7:0]
[7:0] LDAC2PDB
[7:0] ZDPDB
[7:0]
[7:0]
[7:0]
[7:0] RESERVED
[7:0]
[7:0]
[7:0]
[7:0]
[7:0] RESERVED
[7:0]
[7:0]
[7:0] RESERVED
[7:0] LADCPDB
[7:0]
[7:0]
[7:0]
[7:0]
Bit 7
RESERVED
RESERVED
RNSM
LHPMIX6
VBATPWDB
Bit 6
GAINMODE2
ADCRGAIN2
LLINE1MIX6
RLINE1MIX6
LLINE2MIX6
RLINE2MIX6
CDLMIX6
CDRMIX6
RHPMIX6
EPMIX6
DIRCD
MICB1LIM
MICB2LIM
RADCPDB
RADC2PDB
NOCLKDAC2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DPLLA_REF_SEL
DPLLB_REF_SEL
RESERVED
RESERVED
LVL_THR
Bit 5
GAINMODE1
ADCRGAIN1
LLINE1MIX5
RLINE1MIX5
LLINE2MIX5
RLINE2MIX5
CDLMIX5
CDRMIX5
LHPMIX5
RHPMIX5
EPMIX5
MICB1OCEN
MICB2OCEN
MICB2PDB
LDAC1PDB
RESERVED
NOCLKDAC1
MICB2GAIN
POPTIME
RESERVED
PLLA_R
PLLB_R
CDSM
LNSM
Rev. 0 | Page 73 of 296
Bit 4
GAINMODE0
ADCRGAIN0
ADCLMIX4
ADCRMIX4
LLINE1MIX4
RLINE1MIX4
LLINE2MIX4
RLINE2MIX4
CDLMIX4
CDRMIX4
LHPMIX4
RHPMIX4
EPMIX4
HIZ
MICB1CURDEN
MICB2CURDEN
MICB1PDB
RDAC1PDB
EPPDB
PLLA_M_LO
PLLA_N_LO
PLLB_M_LO
PLLB_N_LO
PLLA_M_HI
PLLB_M_HI
PLLA_N_HI
PLLB_N_HI
seven-band EQ block. Refer to the EQ register map (see Table 245)
for using the EQ function. Register addresses are in hexadecimal
format.
Bit 3
INMODE3
ADCLGAIN3
ADCLMIX3
ADCRMIX3
LLINE1MIX3
RLINE1MIX3
LLINE2MIX3
RLINE2MIX3
CDLMIX3
CDRMIX3
LHPMIX3
RHPMIX3
EPMIX3
RCDBST
LDIFF
AIN4PDB
LLN2PDB
LCDPDB
DPLLA_LOCKED
DPLLB_LOCKED
MICB1GAIN
RESERVED
MICB1SHT
MICB2SHT
HPMOD
Bit 2
INMODE2
ADCLGAIN2
ADCLMIX2
ADCRMIX2
LLINE1MIX2
RLINE1MIX2
LLINE2MIX2
RLINE2MIX2
CDLMIX2
CDRMIX2
LHPMIX2
RHPMIX2
EPMIX2
LCDBST
LNFBEN
AIN3PDB
RLN2PDB
RCDPDB
PLLA_LOCKED
PLLB_LOCKED
AIN1LVOL
AIN1RVOL
AIN2LVOL
AIN2RVOL
AIN3LVOL
AIN3RVOL
AIN4LVOL
AIN4RVOL
RLINE1
RLINE2
LLINE1
LLINE2
VOLIM
RCD
LCD
LHP
RHP
DPLLA_NDIV
DPLLB_NDIV
PLLA_X
PLLB_X
Bit 1
INMODE1
ADCLGAIN1
ADCLMIX1
ADCRMIX1
LLINE1MIX1
RLINE1MIX1
LLINE2MIX1
RLINE2MIX1
CDLMIX1
CDRMIX1
LHPMIX1
RHPMIX1
EPMIX1
ZCTO
AIN2PDB
LLN1PDB
HPPDB
DPLLA_BYPASS
DPLLB_BYPASS
MICB1CURD
MICB2CURD
HEADSET
EPGAIN
HPOC
EDGE
Bit 0
INMODE0
ADCLGAIN0
ADCLMIX0
ADCRMIX0
LLINE1MIX0
RLINE1MIX0
LLINE2MIX0
RLINE2MIX0
CDLMIX0
CDRMIX0
LHPMIX0
RHPMIX0
EPMIX0
RESERVED
VMID
AIN1PDB
RLN1PDB
PWDB
PLLA_TYPE
PLLA_EN
PLLB_TYPE
PLLB_EN
NOCLKADC
ADAU1373
Reset RW
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
0x00
0x00
0x00
0x00
0x00
0x00
0x02
0x00
0x00
RW
SRST
SRST
SRST
RW
RW1C
RW1C
RW1C
RW1C
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
SRST
SRST
SRST
SRST
SRST
SRST
SRST
SRST
SRST
SRST
SRST
SRST
SRST
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW
RW
RW
RW
RW
RW
RW
RW