adau1373 Analog Devices, Inc., adau1373 Datasheet - Page 49

• Manufacturer Part Number: adau1373
• Description: Low Power Codec With Speaker And Headphone Amplifier Adau1373
• Manufacturer: Analog Devices, Inc.

SAMPLING RATES
The ADCs, DACs, and DSP share a common sampling rate (f
that is determined based on the core clock rate. Three digital
audio interface ports are available for the ADAU1373. Each port
is provided with an asynchronous sample rate converter (ASRC).
If the ASRCs are used, the sample rate at the digital ports can be
different from the internal sample rate. However, the sample rate
used internally must be equal to or higher than the sample rate
at the ports.
SETTING THE PLL AND CLOCK RATES
For proper operation of the ADAU1373, the device must be set
for correct clock rates. Following are the recommended steps:
Step 1—Sample Rate (f
Determine the desired operating sample rate (f
blocks. f
16 kHz, 8 kHz) or 44.1 kHz (44.1 kHz, 22.05 kHz, 11.025 kHz,
8.0182 kHz). If the ASRCs are bypassed, this is the operating
sample rate at Digital Audio Interface A, Digital Audio Interface B,
and Digital Audio Interface C.
Table 14. 48 kHz Sample Rate (f
Input MCLK
f
256 × f
512 × f
768 × f
1024 × f
Table 15. 44.1 kHz Sample Rate (f
Input MCLK
f
256 × f
512 × f
768 × f
1024 × f
Table 16. 32 kHz Sample Rate (f
Input MCLK
f
256 × f
512 × f
768 × f
1024 × f
1280 × f
1536 × f
IN
IN
IN
S
S
S
S
S
S
S
S
S
(12.288 MHz)
(24.576 MHz)
(36.864 MHz)
S
(11.289 MHz)
(22.5792 MHz)
(33.8688 MHz)
S
(8.192 MHz)
(16.384 MHz)
(24.576 MHz)
S
S
S
S
(49.152 MHz)
(45.1584 MHz)
(32.768 MHz)
(40.96 MHz)
(49.152 MHz)
is based on either 48 kHz (48 kHz, 32 kHz, 24 kHz,
S
Register Setting
CLKxSDIV, Bits[5:3]
000
000
000
000
Register Setting
CLKxSDIV, Bits[5:3]
000
000
000
000
Register Setting
CLKxSDIV, Bits[5:3]
000
000
000
000
000
000
)
S
S
)
)
S
)
S
) for the internal
Divider
K = 0
0
0
0
0
Divider
K = 0
0
0
0
0
Divider
K = 0
0
0
0
0
0
0
S
Rev. 0 | Page 49 of 296
)
Divider Ratio
K + 1
1
1
1
1
Divider Ratio
K + 1
1
1
1
1
1
1
Divider Ratio
K + 1
1
1
1
1
Step 2—Determine Divider J and Divider K
The PLL output or external clock input is divided down to get
the required 256 × f
Bits[5:3], and MCLK1DIV, Bits[2:0] in Register 0x40 for PLLA and
CLK2SDIV, Bits[5:3], and MCLK2DIV, Bits[2:0] in Register 0x42
for PLLB) are provided; each clock divider can be set from 1 to 8.
The CLKxSDIV bits set the K value, and the MCLKxDIV bits
set the J value of the divider. See Figure 93 for more details. See
Table 14, Table 15, and Table 16 for some possible options.
Next, depending on the whether the direct external clock or
PLL is used, select the appropriate equation from the following
sections.
External Mode
In the external mode, the external clock frequency determines
the internal device operation clock rate.
If using external mode,
where D = (J + 1) × (K + 1).
For external clock use, see Table 14, Table 15, and Table 16 for
some possible choices.
Note that clock input frequencies above 50 MHz, although
possible, require careful attention—especially on clock driver
and board layout to maintain signal integrity and lower EMI.
f
IN
= 256 × D × f
Register Setting
MCLKxDIV, Bits[5:3]
000
001
010
011
Register Setting
MCLKxDIV, Bits[5:3]
000
001
010
011
Register Setting
MCLKxDIV, Bits[5:3]
000
001
010
011
100
101
S
core clock. Two clock dividers (CLK1SDIV,
S
Divider
J
0
1
2
3
Divider
J
0
1
2
3
4
5
Divider
J
0
1
2
3
ADAU1373
Divider Ratio
J + 1
1
2
3
4
J + 1
Divider Ratio
J + 1
1
2
3
4
5
6
Divider Ratio
1
2
3
4