adau1373 Analog Devices, Inc., adau1373 Datasheet - Page 22

• Manufacturer Part Number: adau1373
• Description: Low Power Codec With Speaker And Headphone Amplifier Adau1373
• Manufacturer: Analog Devices, Inc.

ADAU1373
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 9. Pin Function Descriptions
Pin
No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
Mnemonic
DGND
MODE
IOVDD4
DMIC_CLK
AIN4R/AIN4N
AIN3R/AIN3N
AIN2R/AIN2N
AIN1R/AIN1N
AVDD
DVDD
ADDR
IOVDD5
DMIC1_2_DATA
AIN4L/AIN4P
AIN3L/AIN3P
AIN2L/AIN2P
AIN1L/AIN1P
CM
Type
PWR
D_IN
PWR
D_OUT
A_IN
A_IN
A_IN
A_IN
PWR
PWR
D_IN
PWR
D_IN
A_IN
A_IN
A_IN
A_IN
A_OUT
A
B
C
D
G
H
J
E
F
Clock Output for Digital Microphone.
Digital Core Supply. Decouple this pin to DGND with a 100 nF capacitor.
Description
Digital Ground. The AGND and DGND pins must be tied directly together in a common ground plane.
Mode Select I
Supply for Digital Microphone Input Port. Set IOVDD4 between 1.8 V and 3.3 V and decouple to
DGND using a 100 nF capacitor.
Right Channel Input 4 (AIN4R)/Inverting Input 4 (AIN4N).
Right Channel Input 3 (AIN3R)/Inverting Input 3 (AIN3N).
Right Channel Input 2 (AIN2R)/Inverting Input 2 (AIN2N).
Right Channel Input 1 (AIN1R)/Inverting Input 1 (AIN1N).
1.5 V to 1.8 V Analog Supply for DAC and Microphone Bias. Decouple this pin to AGND using a 100 nF
capacitor.
Address Setting Pin for I
Supply for I
capacitor.
Serial Data Input Digital Microphone 1 and Serial Data Input Digital Microphone 2.
Left Channel Input 4 (AIN4L)/Noninverting Input 4 (AIN4P).
Left Channel Input 3 (AIN3L)/Noninverting Input 3 (AIN3P).
Left Channel Input 2 (AIN2L)/Noninverting Input 2 (AIN2P).
Left Channel Input 1 (AIN1L)/Noninverting Input 1 (AIN1P).
AVDD/2 V Common-Mode Reference. Connect a 1 μF ceramic decoupling capacitor between this
pin and ground to reduce crosstalk between the ADCs and DACs. This pin can be used to bias
external analog circuits, as long as they are not drawing current from CM (for example, the
noninverting input of an op amp).
BALL A1
CORNER
1
2
2
C Port. Set IOVDD5 between 1.8 V and 3.3 V and decouple to DGND using a 100 nF
2
C Operation. Must be pulled low for I
3
Figure 6. Pin Configuration
Rev. 0 | Page 22 of 296
(BALL SIDE DOWN)
2
C Port. Pull high/low to IOVDD4, using a resistor for the desired chip address.
4
Not to Scale
TOP VIEW
5
6
7
8
2
C mode.
9