mpc8309 Freescale Semiconductor, Inc, mpc8309 Datasheet - Page 68

• Manufacturer Part Number: mpc8309
• Description: Powerquicc Ii Pro Integrated Communications Processor Family Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Clocking
Configuration chapter in the MPC8309 PowerQUICC II Pro Communications Processor Reference
Manual.
The qe_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF])
and the QUICC Engine PLL division factor (RCWL[CEPDF]) as the following equation:
For more information, see the QUICC Engine PLL Multiplication Factor section and the “QUICC Engine
PLL Division Factor” section in the MPC8309 PowerQUICC II Pro Communications Processor
Reference Manual for more information.
The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk.
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that
lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the
external local bus clock outputs (LCLK). The LBC clock divider ratio is controlled by LCCR[CLKDIV].
For more information, see the LBC Bus Clock and Clock Ratios section in the MPC8309 PowerQUICC
II Pro Communications Processor Reference Manual.
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset.
Table 56
“System Clock Control Register (SCCR)” section in the MPC8309 PowerQUICC II Pro Communications
Processor Reference Manual.
Table 57
operating conditions (see
68
I2C,SDHC, USB, DMA Complex
e300 core frequency (core_clk)
Coherent system bus frequency (csb_clk)
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
provides the maximum operating frequencies for the MPC8309 MAPBGA under recommended
specifies which units have a configurable clock frequency. For detailed description, refer to the
Setting the clock ratio of these units must be performed prior to any access
to them.
Unit
Characteristic
Table
qe_clk = (QE_CLK_IN × CEPMF)  (1 + CEPDF)
Table 57. Operating Frequencies for MAPBGA
2).
1
Table 56. Configurable Clock Units
Default Frequency
csb_clk
NOTE
Max Operating Frequency
Off, csb_clk, csb_clk/2, csb_clk/3
417
167
Options
Freescale Semiconductor
MHz
MHz
Unit
Eqn. 3