mpc8309 Freescale Semiconductor, Inc, mpc8309 Datasheet - Page 14

• Manufacturer Part Number: mpc8309
• Description: Powerquicc Ii Pro Integrated Communications Processor Family Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

RESET Initialization
5
This section describes the AC electrical specifications for the reset initialization timing requirements of
the MPC8309.
component(s).
Table 10
5.1
Table 11
14
SYS_CLK_IN duty cycle
SYS_CLK_IN jitter
Notes:
1. Caution: The system, core and QUICC Engine block must not exceed their respective maximum or minimum operating
2. Rise and fall times for SYS_CLK_IN are measured at 0.33 and 2.97 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYS_CLK_IN driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
6. Spread spectrum is allowed upto 1% down-spread @ 33kHz (max rate).
Required assertion time of HRESET to activate reset flow
Required assertion time of PORESET with stable clock applied to
SYS_CLK_IN or PCI_SYNC_IN (in agent mode)
HRESET assertion (output)
Input setup time for POR configuration signals
(CFG_RESET_SOURCE[0:3]) with respect to negation of PORESET
Input hold time for POR config signals with respect to negation of
HRESET
Notes:
1. t
2. POR configuration signals consists of CFG_RESET_SOURCE[0:3].
PLL lock times
frequencies.
allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.
PowerQUICC II Pro Integrated Communications Processor Reference Manual.
SYS_CLK_IN
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
RESET Initialization
provides the DC electrical characteristics for the MPC8309 reset signals mentioned in
provides the PLL lock times.
Reset Signals DC Electrical Characteristics
is the clock period of the input clock applied to SYS_CLK_IN. For more details, see the
Table 9
Parameter/Condition
Parameter/Condition
provides the reset initialization AC timing specifications for the reset
Table 9. RESET Initialization Timing Specifications
Table 8. SYS_CLK_IN AC Timing Specifications
Table 10. PLL Lock Times
t
KHK
/t
SYS_CLK_
—
IN
40
—
Min
—
Min
512
32
32
4
0
—
—
Max
Max
100
—
—
—
—
—
±150
60
Freescale Semiconductor
t
t
t
t
SYS_CLK_IN
SYS_CLK_IN
SYS_CLK_IN
SYS_CLK_IN
MPC8309
Unit
ns
Unit
s
ps
%
Table
Notes
Notes
—
4, 5
1, 2
1, 2
3
1
1
1
9.