cp3ub17 National Semiconductor Corporation, cp3ub17 Datasheet - Page 83

• Manufacturer Part Number: cp3ub17
• Description: Reprogrammable Connectivity Processor With Usb Interface
• Manufacturer: National Semiconductor Corporation

FLUSH
15.3.30 Receive Data 0 Register (RXD0)
Reading the RXD0 register returns the data located at the
current position of the receive read pointer of the Endpoint
0 FIFO. The register allows read-only access from the CPU
bus. After reset, reading this register returns undefined da-
ta.
RXFD
15.3.31 Endpoint Control Register n (EPCn)
Each unidirectional endpoint has an EPCn register. The for-
mat of the EPCn registers is defined below. These registers
provide read/write access from the CPU bus. After reset, the
EPCn registers are clear.
EP
EP_EN
STALL
7
7
Res.
6
Writing 1 to the Flush bit flushes all data from
the control endpoint FIFOs, resets the end-
point to Idle state, clears the FIFO read and
write pointer, and then clears itself. If the end-
point is currently using FIFO0 to transfer data
on USB, flushing is delayed until after the
transfer is done. This bit is cleared on reset.
This bit is equivalent to FLUSH in the TXC0
register.
0 – Writing 0 has no effect.
1 – Writing 1 flushes the FIFOs.
The Receive FIFO Data Byte is used to un-
load the FIFO. Software should expect to read
only the packet payload data. The PID and
CRC16 are removed from the incoming data
stream automatically.
The Endpoint Address field holds the end-
point address.
When the Endpoint Enable bit is set, the
EP[3:0] field is used in address comparison,
together with the AD[6:0] field in the FAR reg-
ister. When clear, the endpoint does not re-
spond to any token on the USB bus. (The
AD_EN bit in the FAR register is the global ad-
dress compare enable for the USB node. If it
is clear, the device does not respond to any
address, without regard to the EP_EN state.)
0 – Address comparison is disabled.
1 – If the AD_EN bit is also set, address com-
parison is enabled.
ISO
5
RXFD7:0
EP_EN
4
3
EP
0
0
83
ISO
STALL
15.3.32 Transmit Status Register n (TXSn)
Each of the three transmit endpoints has a TXSn register.
The format of the TXSn registers is given below. The regis-
ters provide read-only access from the CPU bus. They are
loaded with 1Fh at reset.
TCOUNT
TX_DONE
TX_URUN ACK_STAT TX_DONE
7
When the Isochronous bit is set, the endpoint
is isochronous. This implies that no NAK is
sent if the endpoint is not ready but enabled;
i.e. if an IN token is received and no data is
available in the FIFO to transmit, or if an OUT
token is received and the FIFO is full since
there is no USB handshake for isochronous
transfers.
0 – Isochronous mode disabled.
1 – Isochronous mode enabled.
The Stall bit can be used to enable STALL
handshakes under the following conditions:
A SETUP token does not cause a STALL
handshake to be generated when this bit is
set.
0 – Disable STALL handshakes.
1 – Enable STALL handshakes.
The Transmission Count field reports the
number of empty bytes available in the FIFO.
If this number is greater than 31, a value of 31
is reported.
When set, the Transmission Done bit indi-
cates that the endpoint responded to a USB
packet. Three conditions can cause this bit to
be set:
This bit is cleared when this register is read.
The transmit FIFO is enabled and an IN
token is received.
The receive FIFO is enabled and an OUT
token is received.
A data packet completed transmission in
response to an IN token with non-ISO op-
eration.
The endpoint sent a STALL handshake in
response to an IN token.
A scheduled ISO frame was transmitted or
discarded.
6
5
4
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TCOUNT
0