cp3ub17 National Semiconductor Corporation, cp3ub17 Datasheet - Page 58

• Manufacturer Part Number: cp3ub17
• Description: Reprogrammable Connectivity Processor With Usb Interface
• Manufacturer: National Semiconductor Corporation

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12.5
Altogether, two mechanisms control whether the high-fre-
quency oscillator is active, and three mechanisms control
whether the PLL is active:
12.6
Table 27 lists the power management registers.
12.6.1
The Power Management Control/Status Register (PMMCR)
is a byte-wide, read/write register that controls the operating
power mode (Active, Power Save, Idle, or Halt) and enables
or disables the high-frequency oscillator and PLL in the
Power Save mode. At reset, the non-reserved bits of this
register are cleared. The format of the register is shown be-
low.
PSM
Disable Bits: The DMC and DHC bits in the PMMCR
register may be used to disable the high-frequency oscil-
lator and PLL, respectively, in Power Save mode. THese
bits must be set in Idle and Halt modes.
Power Management Mode: Halt mode disables the
high-frequency oscillator and PLL. Active Mode enables
them. The DMC and DHC bits have no effect in Active or
Halt mode.
PLL Power Down Bit: The PLLPWD bit in the CRCTRL
register can be used to disable the PLL in all modes. This
bit does not affect the high-frequency oscillator.
Reserved
7
PMMCR
PMMSR
Name
Table 27 Power Management Registers
CLOCK CONTROL
POWER MANAGEMENT REGISTERS
Power Management Control Register (PMMCR)
6
If the Power Save Mode bit is clear and the
WBPSM bit is clear, writing 1 to the PSM bit
causes the device to start the switch to Power
Save mode. If the WBPSM bit is set when the
PSM bit is written with 1, entry into Power
Save mode is delayed until execution of a
WAIT instruction. The PSM bit becomes set
after the switch to Power Save mode is com-
plete. The PSM bit can be cleared by soft-
ware, and it can be cleared by hardware when
a hardware wake-up event is detected.
0
1
–
–
DHC DMC WBPSM HALT IDLE PSM
Device is not in Power Save mode.
Device is in Power Save mode.
5
FF FC60h
FF FC62h
Address
4
3
Power Management
Power Management
Control Register
Status Register
Description
2
1
0
58
IDLE
HALT
WBPSM
DMC
DHC
The Idle Mode bit indicates whether the de-
vice has entered Idle mode. The WBPSM bit
must be set to enter Idle mode. When the
IDLE bit is written with 1, the device enters
IDLE mode at the execution of the next WAIT
instruction. The IDLE bit can be set and
cleared by software. It is also cleared by the
hardware when a hardware wake-up event is
detected.
0
1
The Halt Mode bit indicates whether the de-
vice is in Halt mode. Before entering Halt
mode, the WBPSM bit must be set. When the
HALT bit is written with 1, the device enters
the Halt mode at the execution of the next
WAIT instruction. When in HALT mode, the
PMM stops the System Clock and then turns
off the PLL and the high-frequency oscillator.
The HALT bit can be set and cleared by soft-
ware. The Halt mode is exited by a hardware
wake-up event. When this signal is set high,
the oscillator is started. After the oscillator has
stabilized, the HALT bit is cleared by the hard-
ware.
0
1
When the Wait Before Power Save Mode bit is
clear, a switch from Active mode to Power
Save mode only requires setting the PSM bit.
When the WBPSM bit is set, a switch from Ac-
tive mode to Power Save, Idle, or Halt mode is
performed by setting the PSM, IDLE, or HALT
bit, respectively, and then executing a WAIT
instruction. Also, if the DMC or DHC bits are
set, the high-frequency oscillator and PLL
may be disabled only after a WAIT instruction
is executed and the Power Save, Idle, or Halt
mode is entered.
0
1
The Disable Main Clock bit may be used to
disable the high-frequency oscillator in Power
Save mode. In Active mode, the high-frequen-
cy oscillator is enabled without regard to the
DMC value. The DMC bit is cleared by hard-
ware when a hardware wake-up event is de-
tected. This bit must be set in Idle and Halt
modes.
0
1
The Disable High-Frequency (PLL) Clock bit
and may be used to disable the PLL in Power
Save modes. When the DHC bit is clear (and
PLLPWD = 0), the PLL is enabled in Power
Save mode. If the DHC bit is set, the PLL is
disabled in Power Save mode. The DHC bit is
cleared by hardware when a hardware wake-
–
–
–
–
–
–
–
–
Device is not in Idle mode.
Device is in Idle mode.
Device is not in Halt mode.
Device is in Halt mode.
Mode transitions may occur immediately.
Mode transitions are delayed until the
next WAIT instruction is executed.
High-frequency oscillator is not disabled
in Power Save mode.
High-frequency oscillator is disabled in
Power Save mode.