cp3ub17 National Semiconductor Corporation, cp3ub17 Datasheet - Page 3

• Manufacturer Part Number: cp3ub17
• Description: Reprogrammable Connectivity Processor With Usb Interface
• Manufacturer: National Semiconductor Corporation

2.0
CPU Features
On-Chip Memory
Broad Range of Hardware Communications Peripherals
General-Purpose Hardware Peripherals
CP3UB17 Connectivity Processor Selection Guide
T&R = Tape and Reel
CP3UB17G38X
CP3UB17K38X
CP3UB17K38Y
CP3UB17G38
Fully static RISC processor core, capable of operating
from 0 to 24 MHz with zero wait/hold states
Minimum 41.7 ns instruction cycle time with a 24-MHz in-
ternal clock frequency, based on a 12-MHz external input
30 independently vectored peripheral interrupts
256K bytes reprogrammable Flash program memory
8K bytes Flash data memory
10K bytes of static RAM data memory
Addresses up to 8 Mbytes of external memory
Full-speed USB node including seven Endpoint-FIFOs
conforming to USB 1.1 specification
ACCESS.bus serial bus (compatible with Philips I
8/16-bit SPI, Microwire/Plus serial interface
Universal Asynchronous Receiver/Transmitter (UART)
Advanced Audio Interface (AAI) to connect to external 8/
13-bit PCM Codecs as well as to ISDN-Controllers
through the IOM-2 interface (slave only)
CVSD/PCM converter supporting one bidirectional audio
connection
Dual 16-bit Multi-Function Timer
Versatile Timer Unit with four subsystems (VTU)
Four channel DMA controller
Timing and Watchdog Unit
NSID
CPU Features
Speed
(MHz)
24
24
24
24
Temp. Range
-40° to +85°C
-40° to +85°C
-40° to +85°C
-40° to +85°C
Program
(kBytes)
Flash
256
256
256
256
2
C bus)
(kBytes)
Flash
Data
3
8
8
8
8
Flexible I/O
Extensive Power and Clock Management Support
Power Supply
Temperature Range
Packages
Complete Development Environment
Up to 37 general-purpose I/O pins (shared with on-chip
peripheral I/O pins)
Programmable I/O pin characteristics: TRI-STATE out-
put, push-pull output, weak pull-up input, high-imped-
ance input
Schmitt triggers on general purpose inputs
Multi-Input Wakeup
On-chip Phase Locked Loop
Support for multiple clock options
Dual clock and reset
Power-down modes
I/O port operation at 2.5V to 3.3V
Core logic operation at 2.5V
On-chip power-on reset
-40°C to +85°C (Industrial)
CSP-48, LQFP-100
Pre-integrated hardware and software support for rapid
prototyping and production
Integrated environment
Project manager
Multi-file C source editor
(kBytes)
SRAM
10
10
10
10
External
Address
Lines
22
22
0
0
I/Os
37
37
21
21
LQFP-100
LQFP-100 1000-T&R
Package
CSP-48
CSP-48
Type
www.national.com
2500-T&R
250-T&R
Method
Pack
Tray