xe8802 Semtech Corporation, xe8802 Datasheet - Page 62

• Manufacturer Part Number: xe8802
• Description: Data Acquisition Soc With 16+10 Bit Zoomingadc? Embedded Risc Controller And Lcd Driver
• Manufacturer: Semtech Corporation

8.4
The CoolRISC core has 3 different interrupt levels IN0, IN1 and IN2 (Figure 8-1). When these interrupts are
triggered, the program counter (PC) is loaded with a fixed address. In case more than one interrupt occurs
simultaneously, the execution order is IN0, IN1, IN2.
The masking, setting and clearing of these interrupts can be done in the stat register (see chapter describing the
CPU).
The interrupt handler bundles a certain number of interrupt sources and routes them to one of these three
interrupts and provides the possibility to enable/disable each of them individually. The definition of the interrupt
sources is given in the memory mapping chapter.
RegIrqHig, RegIrqMid, and RegIrqLow are 8-bit registers containing flags for the interrupt sources. Those flags are
set when the interrupt is enabled (i.e. if the corresponding bit in the registers RegIrqEnHig, RegIrqEnMid or
RegIrqEnLow is set) and a rising edge is detected on the corresponding interrupt source.
© Semtech 2006
Detailed description
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7-0
7-3
2
1
0
pos.
pos.
pos.
pos.
RegIrqEnMid[7]
RegIrqEnMid[6]
RegIrqEnMid[5]
RegIrqEnMid[4]
RegIrqEnMid[3]
RegIrqEnMid[2]
RegIrqEnMid[1]
RegIrqEnMid[0]
RegIrqEnLow[7]
RegIrqEnLow[6]
RegIrqEnLow[5]
RegIrqEnLow[4]
RegIrqEnLow[3]
RegIrqEnLow[2]
RegIrqEnLow[1]
RegIrqEnLow[0]
RegIrqPriority
-
IrqHig
IrqMid
IrqLow
RegIrqPriority
RegIrqEnLow
RegIrqEnMid
RegIrqIrq
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
r
r
r
r
rw
rw
rw
rw
XE8802 Sensing Machine Data Acquisition MCU
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
11111111
00000
0
0
0
Table 8-8: RegIrqPriority
Table 8-7: RegIrqEnLow
Table 8-6: RegIrqEnMid
Table 8-9: RegIrqIrq
reset
reset
reset
reset
8-4
with ZoomingADC™ and LCD driver
1= enable interrupt #15
1= enable interrupt #14
1= enable interrupt #13
1= enable interrupt #12
1= enable interrupt #11
1= enable interrupt #10
1= enable interrupt #9
1= enable interrupt #8
1= enable interrupt #7
1= enable interrupt #6
1= enable interrupt #5
1= enable interrupt #4
1= enable interrupt #3
1= enable interrupt #2
1= enable interrupt #1
1= enable interrupt #0
code of highest priority set
unused
one or more high priority interrupts is set
one or more mid priority interrupts is set
one or more low priority interrupts is set
function
function
function
function
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