cy8c26233-24sxit Cypress Semiconductor Corporation., cy8c26233-24sxit Datasheet - Page 91

• Manufacturer Part Number: cy8c26233-24sxit
• Description: 8-bit Programmable System-on-chip Psoc? Microcontrollers
• Manufacturer: Cypress Semiconductor Corporation.

10.9.3.4
ARefMux selects the reference input of the A capacitor
branch.
FSW1 is used to control a switch in the integrator capac-
itor path. It connects the output of the op-amp to the inte-
grating cap. The state of the switch is affected by the
state of the AutoZero bit in Control 2 Register
(ASA10CR2, ASA12CR2, ASA21CR2, ASA23CR2). If
the FSW1 bit is set to 0, the switch is always disabled. If
the FSW1 bit is set to 1, the AutoZero bit determines the
state of the switch. If the AutoZero bit is 0, the switch is
Table 71:
Analog Switch Cap Type A Block 10 Control 3 Register (ASA10CR3, Address = Bank 0/1, 83h)
Analog Switch Cap Type A Block 12 Control 3 Register (ASA12CR3, Address = Bank 0/1, 8Bh)
Analog Switch Cap Type A Block 21 Control 3 Register (ASA21CR3, Address = Bank 0/1, 97h)
Analog Switch Cap Type A Block 23 Control 3 Register (ASA23CR3, Address = Bank 0/1, 9Fh)
September 5, 2002
Bit [7:6] : ARefMux [1:0] Encoding for selecting reference input
0 0 = Analog ground is selected
0 1 = REFHI input selected (This is usually the high reference)
1 0 = REFLO input selected (This is usually the low reference)
1 1 = Reference selection is driven by the comparator (When output comparator node is set high, the input is set to
REFHI. When set low, the input is set to REFLO)
Bit 5 : FSW1 Bit for controlling gated switches
0 = Switch is disabled
1 = If the FSW1 bit is set to 1, the state of the switch is determined by the AutoZero bit. If the AutoZero bit is 0, the
switch is enabled at all times. If the AutoZero bit is 1, the switch is enabled only when the internal PHI2 is high
Bit 4 : FSW0 Bits for controlling gated switches
0 = Switch is disabled
1 = Switch is enabled when PHI1 is high
Bit [3:2] BMuxSCA [1:0] Encoding for selecting B inputs. (Note that the available mux inputs vary by individual
PSoC block.)
0 0 = ACA00
0 1 = ASB11
1 0 = P2.3
1 1 = ASB20 T
Bit [1:0] : Power [1:0] Encoding for selecting 1 of 4 power levels
0 0 = Off
0 1 = 10 µ A, typical
1 0 = 50 µ A, typical
1 1 = 200 µ A, typical
Bit Name
Read/
Write
Bit #
POR
ASA10
Analog Switch Cap Type A Block xx Control 3 Register
Analog Switch Cap Type A Block xx Control 3 Register
ARefMux[1] ARefMux[0]
ASB22
ASB20
ASB11
ASA21
ref
RW
7
0
GND ASB22
ASA12
ACA02
ASB13
ASB11
RW
6
0
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
ASA23
ASB13
ASB22
ABUS3
P2.0
FSW[1]
RW
5
0
FSW[0]
RW
4
0
enabled at all times. If the AutoZero bit is 1, the switch is
enabled only when the internal PHI2 is high.
FSW0 is used to control a switch in the integrator capac-
itor path. It connects the output of the op-amp to analog
ground.
BMuxSCA controls the muxing to the input of the B
capacitor branch.
Power – encoding for selecting 1 of 4 power levels. The
block always powers up in the off state.
BMuxSCA[1]
RW
3
0
BMuxSCA[0]
RW
2
0
Power[1]
RW
Analog PSoC Blocks
1
0
Power[0]
RW
0
0
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