cy8c26233-24sxit Cypress Semiconductor Corporation., cy8c26233-24sxit Datasheet - Page 54

• Manufacturer Part Number: cy8c26233-24sxit
• Description: 8-bit Programmable System-on-chip Psoc? Microcontrollers
• Manufacturer: Cypress Semiconductor Corporation.

Table 51:
9.3
There are four user registers within each digital PSoC
block: three data registers, and one status/control regis-
ter. The three data registers are DR0, which is a shifter/
counter, and DR1 and DR2 registers, which contain data
9.3.1
Table 52:
Bit [7:0] : Data [7:0]
1.
Digital Basic Type A Block 00 Data Register 0
Digital Basic Type A Block 00 Data Register 1
Digital Basic Type A Block 00 Data Register 2
Digital Basic Type A Block 01 Data Register 0
Digital Basic Type A Block 01 Data Register 1
Digital Basic Type A Block 01 Data Register 2
Digital Basic Type A Block 02 Data Register 0
Digital Basic Type A Block 02 Data Register 1
Digital Basic Type A Block 02 Data Register 2
Digital Basic Type A Block 03 Data Register 0
Digital Basic Type A Block 03 Data Register 1
Digital Basic Type A Block 03 Data Register 2
Digital Communications Type A Block 04 Data Register 0
Digital Communications Type A Block 04 Data Register 1
Digital Communications Type A Block 04 Data Register 2
Digital Communications Type A Block 05 Data Register 0
Digital Communications Type A Block 05 Data Register 1
Digital Communications Type A Block 05 Data Register 2
Digital Communications Type A Block 06 Data Register 0
Digital Communications Type A Block 06 Data Register 1
54
Read/Write
Timer
Counter
CRC
PRS
Deadband
TX UART
RX UART
SPI Master
SPI Slave
Bit Name
Function
Bit #
POR
Varies by function/User Module selection. (See
Digital PSoC Block Bank 0 Registers
Digital Function Outputs
Digital Basic Type A / Communications Type A Block xx Data Register 0,1,2
Digital Basic Type A / Communications Type A Block xx Data Register 0,1,2
Data [7]
Terminal Count
Compare True
N/A
Serial Data
F0
TX Data Out
N/A
MOSI
MISO
VF
Primary Output
7
0
1
Data [6]
VF
6
0
1
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
Compare True
Terminal Count
Compare True
Compare True
F1
N/A
N/A
SCLK
N/A
Auxiliary Output
Data [5]
VF
5
0
1
Table 53 on page
Data [4]
VF
4
0
1
used during the operation. The status/control register
(CR0) contains an enable bit that is used for all configu-
rations. In addition, it contains function-specific status
and control, which is outlined below.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
SS_
(DBA00DR0, Address = Bank 0, 20h)
(DBA00DR1, Address = Bank 0, 21h)
(DBA00DR2, Address = Bank 0, 22h)
(DBA01DR0, Address = Bank 0, 24h)
(DBA01DR1, Address = Bank 0, 25h)
(DBA01DR2, Address = Bank 0, 26h)
(DBA02DR0, Address = Bank 0, 28h)
(DBA02DR1, Address = Bank 0, 29h)
(DBA02DR2, Address = Bank 0, 2Ah)
(DBA03DR0, Address = Bank 0, 2Ch)
(DBA03DR1, Address = Bank 0, 2Dh)
(DBA03DR2, Address = Bank 0, 2Eh)
(DCA04DR0, Address = Bank 0, 30h)
(DCA04DR1, Address = Bank 0, 31h)
(DCA04DR2, Address = Bank 0, 32h)
(DCA05DR0, Address = Bank 0, 34h)
(DCA05DR1, Address = Bank 0, 35h)
(DCA05DR2, Address = Bank 0, 36h)
(DCA06DR0, Address = Bank 0, 38h)
(DCA06DR1, Address = Bank 0, 39h)
Auxiliary Input
Data [3]
VF
55.)
3
0
1
Data [2]
VF
2
0
1
Data [1]
VF
1
0
1
September 5, 2002
Data [0]
VF
0
0
1