xc4025 Xilinx Corp., xc4025 Datasheet - Page 3

• Manufacturer Part Number: xc4025
• Description: Logic Cell Array Family , Inc
• Manufacturer: Xilinx Corp.

Wide Decoder Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Note: These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (T
Description
Full length, both pull-ups,
inputs from IOB I-pins
Full length, both pull-ups
inputs from internal logic
Half length, one pull-up
inputs from IOB I-pins
Half length, one pull-up
inputs from internal logic
and output delay (T
PRELIMINARY
OPF
or T
OPS
), as listed on page 2-52.
T
T
T
T
Symbol
WAF
WAFL
WAO
WAOL
Speed Grade
Device
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
2-49
Max
10.0
11.0
12.0
13.0
15.0
21.0
12.0
13.0
14.0
15.0
16.0
18.0
24.0
10.0
11.0
12.0
13.0
15.0
21.0
12.0
13.0
14.0
15.0
16.0
18.0
24.0
-6
9.0
9.0
Max
10.0
11.0
12.0
14.0
19.0
11.0
12.0
13.0
14.0
15.0
17.0
23.0
10.0
11.0
12.0
14.0
19.0
11.0
12.0
13.0
14.0
15.0
17.0
23.0
-5
8.0
8.0
9.0
9.0
Max
11.0
17.0
10.0
11.0
13.0
20.0
10.0
12.0
18.0
10.0
11.0
12.0
14.0
21.0
-4
5.0
6.0
7.0
8.0
9.0
7.0
8.0
9.0
6.0
7.0
8.0
9.0
8.0
9.0
Units
PID
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
)