xc4025 Xilinx Corp., xc4025 Datasheet

xc4025

Manufacturer Part Number

xc4025

Description

Logic Cell Array Family , Inc

Manufacturer

Xilinx Corp.

Datasheet

1.XC4025.pdf (22 pages)

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*XC4010D has no RAM

Table 1. The XC4000 Family of Field-Programmable Gate Arrays

Features

•

Device

Appr. Gate Count

CLB Matrix

Number of CLBs

Number of Flip-Flops

Max Decode Inputs (per side)

Max RAM Bits

Number of IOBs

Third Generation Field-Programmable Gate Arrays

– Abundant flip-flops

– Flexible function generators

– On-chip ultra-fast RAM

– Dedicated high-speed carry-propagation circuit

– Wide edge decoders (four per edge)

– Hierarchy of interconnect lines

– Internal 3-state bus capability

– Eight global low-skew clock or signal distribution

Flexible Array Architecture

– Programmable logic blocks and I/O blocks

– Programmable interconnects and wide decoders

Sub-micron CMOS Process

– High-speed logic and Interconnect

– Low power consumption

Systems-Oriented Features

– IEEE 1149.1-compatible boundary-scan logic support

– Programmable output slew rate (2 modes)

– Programmable input pull-up or pull-down resistors

– 12-mA sink current per output

– 24-mA sink current per output pair

Configured by Loading Binary File

– Unlimited reprogrammability

– Six programming modes

XACT Development System runs on ’386/’486-type PC,

NEC PC, Apollo, Sun-4, and Hewlett-Packard 700

series

– Interfaces to popular design environments like

– Fully automatic partitioning, placement and routing

– Interactive design editor for design optimization

– 288 macros, 34 hard macros, RAM/ROM compiler

network

Viewlogic, Mentor Graphics and OrCAD

XC4003

10 x 10

3,000

3,200

100

360

XC4005

14 x 14

5,000

6,272

196

616

112

XC4006

16 x 16

6,000

8,192

256

768

128

2-47

XC4000

Logic Cell Array Family

Product Specifications

Description

The XC4000 family of Field-Programmable Gate Arrays

The XC4000 family provides a regular, flexible, program-

XC4000 devices have generous routing resources to ac-

The XC4000 family is supported by powerful and sophisti-

Since Xilinx FPGAs can be reprogrammed an unlimited

For a detailed description of the device features, architec-

(FPGAs) provides the benefits of custom CMOS VLSI,

while avoiding the initial cost, time delay, and inherent risk

of a conventional masked gate array.

mable architecture of Configurable Logic Blocks (CLBs),

interconnected by a powerful hierarchy of versatile routing

resources, and surrounded by a perimeter of program-

mable Input/Output Blocks (IOBs).

commodate the most complex interconnect patterns. They

are customized by loading configuration data into the inter-

nal memory cells. The FPGA can either actively read its

configuration data out of external serial or byte-parallel

PROM (master modes), or the configuration data can be

written into the FPGA (slave and peripheral modes).

cated software, covering every aspect of design: from

schematic entry, to simulation, to automatic block place-

ment and routing of interconnects, and finally the creation

of the configuration bit stream.

number of times, they can be used in innovative designs

where hardware is changed dynamically, or where hard-

ware must be adapted to different user applications. FPGAs

are ideal for shortening the design and development cycle,

but they also offer a cost-effective solution for production

rates well beyond 1000 systems per month.

ture, configuration methods and pin descriptions, see

pages 2-9 through 2-45.

XC4008 XC4010/10D

18 x 18

10,368

8,000

324

936

144

12,800*

20 x 20

10,000

1,120

400

160

XC4013

24 x 24

13,000

18,432

1,536

576

192

XC4020

28 x 28

20,000

25,088

2,016

784

224

XC4025

32 x 32

25,000

32,768

1,024

2,560

256

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xc4025 Summary of contents

Page 1

... XC4013 XC4020 10,000 13,000 20,000 400 576 784 1,120 1,536 2,016 12,800* 18,432 25,088 160 192 224 XC4025 25,000 1,024 2,560 96 32,768 256 ...

XC4000 Logic Cell Array Family Absolute Maximum Ratings Symbol Description V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Maximum soldering ...

Page 3

... Speed Grade Symbol Device Max T XC4003 WAF XC4005 10.0 XC4006 11.0 XC4008 12.0 XC4010 13.0 XC4013 15.0 XC4025 21.0 T XC4003 12.0 WAFL XC4005 13.0 XC4006 14.0 XC4008 15.0 XC4010 16.0 XC4013 18.0 XC4025 24.0 T XC4003 WAO XC4005 10.0 XC4006 11.0 XC4008 12.0 XC4010 13.0 XC4013 15.0 XC4025 21.0 T XC4003 12.0 WAOL XC4005 13.0 XC4006 14.0 XC4008 15.0 XC4010 16.0 XC4013 18.0 XC4025 24.0 2- Max Max Units 9.0 8.0 5.0 9.0 6.0 10.0 7.0 11.0 8.0 12.0 9.0 14.0 11.0 19.0 17.0 11.0 7.0 12.0 8.0 13.0 9.0 14.0 10.0 15.0 11.0 17.0 13.0 23.0 20.0 9.0 8.0 6.0 9.0 7.0 10.0 8.0 11.0 9.0 12.0 10.0 14.0 12.0 19.0 18.0 11.0 8.0 12.0 9.0 13.0 10.0 14.0 11.0 15.0 12.0 17.0 14 ...

Page 4

... IO2 XC4005 10.5 XC4006 11.1 XC4008 11.6 XC4010 12.2 XC4013 13.5 XC4025 23.5 T XC4003 10.7 ON XC4005 12.0 XC4006 12.6 XC4008 13.2 XC4010 13.8 XC4013 15.1 XC4025 23.0 T All devices 3.0 OFF T XC4003 24.0 PUS XC4005 26.0 XC4006 28.0 XC4008 30.0 XC4010 32.0 XC4013 36.0 XC4025 52.0 T XC4003 11.6 PUF XC4005 12.0 XC4006 13.0 XC4008 14.0 XC4010 15.0 XC4013 17.0 XC4025 24.0 2- Max Max Units 5.8 5.1 ns 6.0 5.5 ns 6.2 5.7 ns 6.6 6.1 ns 7.0 6.5 ns 8.0 7.5 ns 15.0 14.5 ns 6.8 6 ...

Page 5

... T for -4 Speed Grade PDLI XC4003 17.6 ns Pad to I1, I2 XC4005 17.9 ns via transparent XC4006 18.0 ns latch, with delay XC4008 18.3 ns XC4010 18.6 ns XC4013 19.3 ns XC4025 23.5 ns PRELIMINARY Speed Grade Symbol T XC4003 ICKOF XC4005 . XC4006 . (Max) XC4008 . ...

Page 6

XC4000 Logic Cell Array Family IOB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived ...

Page 7

CLB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The ...

Page 8

XC4000 Logic Cell Array Family CLB Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are ...

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xc4025 Xilinx Corp., xc4025 Datasheet

xc4025

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xc4025 Summary of contents

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